559 lines
16 KiB
C
559 lines
16 KiB
C
/*
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* -- Version 1.1 --
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*
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* (C) Copyright 2003-2005
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2004-2005
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* Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
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*
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* (C) Copyright 2005
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* Stefan Strobl, GERSYS GmbH, stefan.strobl@gersys.de.
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*
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* History:
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* 1.1 - add define CONFIG_ZERO_BOOTDELAY_CHECK
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
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#define CONFIG_MPC5200 1 /* (more precisely a MPC5200 CPU) */
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#define CONFIG_TQM5200 1 /* ... on a TQM5200 module */
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#define CONFIG_BC3450 1 /* ... on a BC3450 mainboard */
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#define CONFIG_BC3450_PS2 1 /* + a PS/2 converter onboard */
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#define CONFIG_BC3450_IDE 1 /* + IDE drives (Compact Flash) */
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#define CONFIG_BC3450_USB 1 /* + USB support */
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# define CONFIG_FAT 1 /* + FAT support */
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# define CONFIG_EXT2 1 /* + EXT2 support */
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#undef CONFIG_BC3450_BUZZER /* + Buzzer onboard */
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#undef CONFIG_BC3450_CAN /* + CAN transceiver */
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#undef CONFIG_BC3450_DS1340 /* + a RTC DS1340 onboard */
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#undef CONFIG_BC3450_DS3231 /* + a RTC DS3231 onboard tbd */
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#undef CONFIG_BC3450_AC97 /* + AC97 on PSC2, tbd */
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#define CONFIG_BC3450_FP 1 /* + enable FP O/P */
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#undef CONFIG_BC3450_CRT /* + enable CRT O/P (Debug only!) */
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#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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#define CONFIG_HIGH_BATS 1 /* High BATs supported */
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/*
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* Serial console configuration
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*/
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#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
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#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
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/*
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* AT-PS/2 Multiplexer
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*/
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#ifdef CONFIG_BC3450_PS2
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# define CONFIG_PS2KBD /* AT-PS/2 Keyboard */
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# define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */
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# define CONFIG_PS2SERIAL 6 /* .. on PSC6 */
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# define CONFIG_PS2MULT_DELAY (CFG_HZ/2) /* Initial delay */
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# define CONFIG_BOARD_EARLY_INIT_R
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#endif /* CONFIG_BC3450_PS2 */
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/*
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* PCI Mapping:
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* 0x40000000 - 0x4fffffff - PCI Memory
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* 0x50000000 - 0x50ffffff - PCI IO Space
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*/
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# define CONFIG_PCI 1
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# define CONFIG_PCI_PNP 1
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/* #define CONFIG_PCI_SCAN_SHOW 1 */
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#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
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#define CONFIG_PCI_MEM_BUS 0x40000000
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#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
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#define CONFIG_PCI_MEM_SIZE 0x10000000
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#define CONFIG_PCI_IO_BUS 0x50000000
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#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
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#define CONFIG_PCI_IO_SIZE 0x01000000
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#define CONFIG_NET_MULTI 1
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/*#define CONFIG_EEPRO100 XXX - FIXME: conflicts when CONFIG_MII is enabled */
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#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
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#define CONFIG_NS8382X 1
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/*
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* Video console
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*/
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# define CONFIG_VIDEO
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# define CONFIG_VIDEO_SM501
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# define CONFIG_VIDEO_SM501_32BPP
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# define CONFIG_CFB_CONSOLE
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# define CONFIG_VIDEO_LOGO
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# define CONFIG_VGA_AS_SINGLE_DEVICE
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# define CONFIG_CONSOLE_EXTRA_INFO /* display Board/Device-Infos */
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# define CONFIG_VIDEO_SW_CURSOR
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# define CONFIG_SPLASH_SCREEN
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# define CFG_CONSOLE_IS_IN_ENV
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/*
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* Partitions
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*/
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#define CONFIG_MAC_PARTITION
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#define CONFIG_DOS_PARTITION
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#define CONFIG_ISO_PARTITION
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/*
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* USB
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*/
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#ifdef CONFIG_BC3450_USB
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# define CONFIG_USB_OHCI
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# define CONFIG_USB_STORAGE
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#endif /* CONFIG_BC3450_USB */
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/*
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* POST support
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*/
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#define CONFIG_POST (CFG_POST_MEMORY | \
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CFG_POST_CPU | \
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CFG_POST_I2C)
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#ifdef CONFIG_POST
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/* preserve space for the post_word at end of on-chip SRAM */
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# define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
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#endif /* CONFIG_POST */
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_ASKENV
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_ECHO
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#define CONFIG_CMD_EEPROM
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_JFFS2
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_NFS
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_REGINFO
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#define CONFIG_CMD_SNTP
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#define CONFIG_CMD_BSP
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#ifdef CONFIG_VIDEO
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#define CONFIG_CMD_BMP
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#endif
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#ifdef CONFIG_BC3450_IDE
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#define CONFIG_CMD_IDE
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#endif
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#if defined(CONFIG_BC3450_IDE) || defined(CONFIG_BC3450_USB)
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#ifdef CONFIG_FAT
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#define CONFIG_CMD_FAT
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#endif
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#ifdef CONFIG_EXT2
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#define CONFIG_CMD_EXT2
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#endif
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#endif
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#ifdef CONFIG_BC3450_USB
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#define CONFIG_CMD_USB
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#endif
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#ifdef CONFIG_PCI
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#define CONFIG_CMD_PCI
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#endif
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#ifdef CONFIG_POST
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#define CONFIG_CMD_DIAG
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#endif
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#define CONFIG_TIMESTAMP /* display image timestamps */
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#if (TEXT_BASE == 0xFC000000) /* Boot low */
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# define CFG_LOWBOOT 1
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#endif
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/*
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* Autobooting
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*/
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
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#define CONFIG_PREBOOT "echo;" \
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"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
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"echo;"
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#undef CONFIG_BOOTARGS
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=eth0\0" \
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"ipaddr=192.168.1.10\0" \
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"serverip=192.168.1.3\0" \
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"netmask=255.255.255.0\0" \
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"hostname=bc3450\0" \
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"rootpath=/opt/eldk/ppc_6xx\0" \
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"kernel_addr=fc0a0000\0" \
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"ramdisk_addr=fc1c0000\0" \
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"ramargs=setenv bootargs root=/dev/ram rw\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=$(serverip):$(rootpath)\0" \
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"ideargs=setenv bootargs root=/dev/hda2 ro\0" \
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"addip=setenv bootargs $(bootargs) " \
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"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
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":$(hostname):$(netdev):off panic=1\0" \
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"addcons=setenv bootargs $(bootargs) " \
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"console=ttyS0,$(baudrate) console=tty0\0" \
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"flash_self=run ramargs addip addcons;" \
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"bootm $(kernel_addr) $(ramdisk_addr)\0" \
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"flash_nfs=run nfsargs addip addcons; bootm $(kernel_addr)\0" \
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"net_nfs=tftp 200000 $(bootfile); " \
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"run nfsargs addip addcons; bootm\0" \
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"ide_nfs=run nfsargs addip addcons; " \
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"disk 200000 0:1; bootm\0" \
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"ide_ide=run ideargs addip addcons; " \
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"disk 200000 0:1; bootm\0" \
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"usb_self=run usbload; run ramargs addip addcons; " \
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"bootm 200000 400000\0" \
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"usbload=usb reset; usb scan; usbboot 200000 0:1; " \
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"usbboot 400000 0:2\0" \
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"bootfile=uImage\0" \
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"load=tftp 200000 $(u-boot)\0" \
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"u-boot=u-boot.bin\0" \
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"update=protect off FC000000 FC05FFFF;" \
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"erase FC000000 FC05FFFF;" \
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"cp.b 200000 FC000000 $(filesize);" \
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"protect on FC000000 FC05FFFF\0" \
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""
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#define CONFIG_BOOTCOMMAND "run flash_self"
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/*
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* IPB Bus clocking configuration.
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*/
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#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
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/*
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* PCI Bus clocking configuration
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*
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* Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
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* CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
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* of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
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*/
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#if defined(CFG_IPBCLK_EQUALS_XLBCLK)
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# define CFG_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
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#endif
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/*
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* I2C configuration
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*/
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#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
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#define CFG_I2C_MODULE 2 /* Select I2C module #2 */
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/*
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* I2C clock frequency
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*
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* Please notice, that the resulting clock frequency could differ from the
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* configured value. This is because the I2C clock is derived from system
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* clock over a frequency divider with only a few divider values. U-boot
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* calculates the best approximation for CFG_I2C_SPEED. However the calculated
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* approximation allways lies below the configured value, never above.
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*/
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#define CFG_I2C_SPEED 100000 /* 100 kHz */
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#define CFG_I2C_SLAVE 0x7F
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/*
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* EEPROM configuration for I²C EEPROM M24C32
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* M24C64 should work also. For other EEPROMs config should be verified.
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*
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* The TQM5200 module may hold an EEPROM at address 0x50.
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*/
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#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x (TQM) */
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#define CFG_I2C_EEPROM_ADDR_LEN 2
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#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
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#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70
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/*
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* RTC configuration
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*/
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#if defined (CONFIG_BC3450_DS1340) && !defined (CONFIG_BC3450_DS3231)
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# define CONFIG_RTC_M41T11 1
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# define CFG_I2C_RTC_ADDR 0x68
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#else
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# define CONFIG_RTC_MPC5200 1 /* use MPC5200 internal RTC */
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# define CONFIG_BOARD_EARLY_INIT_R
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#endif
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/*
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* Flash configuration
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*/
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#define CFG_FLASH_BASE TEXT_BASE /* 0xFC000000 */
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/* use CFI flash driver if no module variant is spezified */
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#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
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#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
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#define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START }
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#define CFG_FLASH_EMPTY_INFO
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#define CFG_FLASH_SIZE 0x04000000 /* 64 MByte */
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#define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */
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#undef CFG_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */
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#if !defined(CFG_LOWBOOT)
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#define CONFIG_ENV_ADDR (CFG_FLASH_BASE + 0x00760000 + 0x00800000)
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#else /* CFG_LOWBOOT */
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#define CONFIG_ENV_ADDR (CFG_FLASH_BASE + 0x00060000)
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#endif /* CFG_LOWBOOT */
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#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks
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(= chip selects) */
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#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
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/* Dynamic MTD partition support */
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#define CONFIG_JFFS2_CMDLINE
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#define MTDIDS_DEFAULT "nor0=TQM5200-0"
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#define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \
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"1408k(kernel)," \
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"2m(initrd)," \
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"4m(small-fs)," \
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"16m(big-fs)," \
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"8m(misc)"
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/*
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* Environment settings
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*/
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_SIZE 0x10000
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#define CONFIG_ENV_SECT_SIZE 0x20000
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#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
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/*
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* Memory map
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*/
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#define CFG_MBAR 0xF0000000
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#define CFG_SDRAM_BASE 0x00000000
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#define CFG_DEFAULT_MBAR 0x80000000
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/* Use ON-Chip SRAM until RAM will be available */
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#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
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#ifdef CONFIG_POST
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/* preserve space for the post_word at end of on-chip SRAM */
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# define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
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#else
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# define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE
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#endif /*CONFIG_POST*/
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#define CFG_GBL_DATA_SIZE 128 /* Bytes reserved for initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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#define CFG_MONITOR_BASE TEXT_BASE
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#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
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# define CFG_RAMBOOT 1
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#endif
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#define CFG_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
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#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*
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* Ethernet configuration
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*
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* Define CONFIG_FEC10MBIT to force FEC at 10MBIT
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*/
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#define CONFIG_MPC5xxx_FEC 1
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#undef CONFIG_FEC_10MBIT
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#define CONFIG_PHY_ADDR 0x00
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/*
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* GPIO configuration on BC3450
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*
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* PSC1: UART1 (Service-UART) [0x xxxxxxx4]
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* PSC2: UART2 [0x xxxxxx4x]
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* or: AC/97 if CONFIG_BC3450_AC97 [0x xxxxxx2x]
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* PSC3: USB2 [0x xxxxx1xx]
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* USB: UART4(ext.)/UART5(int.) [0x xxxx2xxx]
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* (this has to match
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* CONFIG_USB_CONFIG which is
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* used by usb_ohci.c to set
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* the USB ports)
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* Eth: 10/100Mbit Ethernet [0x xxx0xxxx]
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* (this is reset to '5'
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* in FEC driver: fec.c)
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* PSC6: UART6 (int. to PS/2 contr.) [0x xx5xxxxx]
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* ATA/CS: ??? [0x x1xxxxxx]
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* FIXME! UM Fig 2-10 suggests [0x x0xxxxxx]
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* CS1: Use Pin gpio_wkup_6 as second
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* SDRAM chip select (mem_cs1)
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* Timer: CAN2 / SPI
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* I2C: CAN1 / I²C2 [0x bxxxxxxx]
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*/
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#ifdef CONFIG_BC3450_AC97
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# define CFG_GPS_PORT_CONFIG 0xb1502124
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#else /* PSC2=UART2 */
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# define CFG_GPS_PORT_CONFIG 0xb1502144
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#endif
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#if defined(CONFIG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max no of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Arg. Buffer Size */
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#define CFG_ALT_MEMTEST /* Enable an alternative, */
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/* more extensive mem test */
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#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
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#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
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#define CFG_LOAD_ADDR 0x100000 /* default load address */
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#define CFG_HZ 1000 /* dec freq: 1ms ticks */
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#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
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#if defined(CONFIG_CMD_KGDB)
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# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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#endif
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/*
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* Enable loopw command.
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*/
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#define CONFIG_LOOPW
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/*
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* Various low-level settings
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*/
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#if defined(CONFIG_MPC5200)
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# define CFG_HID0_INIT HID0_ICE | HID0_ICFI
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# define CFG_HID0_FINAL HID0_ICE
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#else
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# define CFG_HID0_INIT 0
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# define CFG_HID0_FINAL 0
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#endif
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#define CFG_BOOTCS_START CFG_FLASH_BASE
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#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
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#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2
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# define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
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#else
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# define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
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#endif
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#define CFG_CS0_START CFG_FLASH_BASE
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#define CFG_CS0_SIZE CFG_FLASH_SIZE
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/* automatic configuration of chip selects */
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#ifdef CONFIG_TQM5200
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# define CONFIG_LAST_STAGE_INIT
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#endif /* CONFIG_TQM5200 */
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/*
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* SRAM - Do not map below 2 GB in address space, because this area is used
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* for SDRAM autosizing.
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*/
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#ifdef CONFIG_TQM5200
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# define CFG_CS2_START 0xE5000000
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# define CFG_CS2_SIZE 0x100000 /* 1 MByte */
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# define CFG_CS2_CFG 0x0004D930
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#endif /* CONFIG_TQM5200 */
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/*
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* Grafic controller - Do not map below 2 GB in address space, because this
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* area is used for SDRAM autosizing.
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*/
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#ifdef CONFIG_TQM5200
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# define SM501_FB_BASE 0xE0000000
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# define CFG_CS1_START (SM501_FB_BASE)
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# define CFG_CS1_SIZE 0x4000000 /* 64 MByte */
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# define CFG_CS1_CFG 0x8F48FF70
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# define SM501_MMIO_BASE CFG_CS1_START + 0x03E00000
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#endif /* CONFIG_TQM5200 */
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#define CFG_CS_BURST 0x00000000
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#define CFG_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for */
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/* flash and SM501 */
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#define CFG_RESET_ADDRESS 0xff000000
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/*
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* USB stuff
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*/
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#define CONFIG_USB_CLOCK 0x0001BBBB
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#define CONFIG_USB_CONFIG 0x00002000 /* we're using Port 2 */
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/*
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* IDE/ATA stuff Supports IDE harddisk
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*/
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#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
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#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
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#undef CONFIG_IDE_LED /* LED for ide not supported */
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|
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#define CONFIG_IDE_RESET /* reset for ide supported */
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#define CONFIG_IDE_PREINIT
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#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
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#define CFG_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
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#define CFG_ATA_IDE0_OFFSET 0x0000
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#define CFG_ATA_BASE_ADDR MPC5XXX_ATA
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/* Offset for data I/O */
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#define CFG_ATA_DATA_OFFSET (0x0060)
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/* Offset for normal register accesses */
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#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
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/* Offset for alternate registers */
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#define CFG_ATA_ALT_OFFSET (0x005C)
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/* Interval between registers */
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#define CFG_ATA_STRIDE 4
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#endif /* __CONFIG_H */
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