65cc0e2a65
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
145 lines
3.3 KiB
C
145 lines
3.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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#include <asm/io.h>
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#include <common.h>
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#include <div64.h>
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#include <dm/device.h>
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#include <dm/fdtaddr.h>
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#include <timer.h>
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#define TIMER_CTRL 0x00
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#define TIMER0_EN BIT(0)
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#define TIMER0_RELOAD_EN BIT(1)
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#define TIMER0_RELOAD 0x10
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#define TIMER0_VAL 0x14
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enum input_clock_type {
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INPUT_CLOCK_NON_FIXED,
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INPUT_CLOCK_25MHZ, /* input clock rate is fixed to 25MHz */
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};
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struct orion_timer_priv {
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void *base;
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};
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#define MVEBU_TIMER_FIXED_RATE_25MHZ 25000000
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static bool early_init_done __section(".data") = false;
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/* Common functions for early (boot) and DM based timer */
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static void orion_timer_init(void *base, enum input_clock_type type)
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{
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/* Only init the timer once */
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if (early_init_done)
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return;
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early_init_done = true;
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writel(~0, base + TIMER0_VAL);
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writel(~0, base + TIMER0_RELOAD);
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if (type == INPUT_CLOCK_25MHZ) {
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/*
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* On Armada XP / 38x ..., the 25MHz clock source needs to
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* be enabled
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*/
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setbits_le32(base + TIMER_CTRL, BIT(11));
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}
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/* enable timer */
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setbits_le32(base + TIMER_CTRL, TIMER0_EN | TIMER0_RELOAD_EN);
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}
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static uint64_t orion_timer_get_count(void *base)
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{
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return timer_conv_64(~readl(base + TIMER0_VAL));
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}
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/* Early (e.g. bootstage etc) timer functions */
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static void notrace timer_early_init(void)
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{
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if (IS_ENABLED(CONFIG_ARCH_MVEBU))
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orion_timer_init((void *)MVEBU_TIMER_BASE, INPUT_CLOCK_25MHZ);
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else
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orion_timer_init((void *)MVEBU_TIMER_BASE, INPUT_CLOCK_NON_FIXED);
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}
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/**
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* timer_early_get_rate() - Get the timer rate before driver model
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*/
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unsigned long notrace timer_early_get_rate(void)
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{
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timer_early_init();
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if (IS_ENABLED(CONFIG_ARCH_MVEBU))
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return MVEBU_TIMER_FIXED_RATE_25MHZ;
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else
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return CFG_SYS_TCLK;
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}
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/**
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* timer_early_get_count() - Get the timer count before driver model
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*
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*/
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u64 notrace timer_early_get_count(void)
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{
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timer_early_init();
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return orion_timer_get_count((void *)MVEBU_TIMER_BASE);
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}
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ulong timer_get_boot_us(void)
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{
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u64 ticks;
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ticks = timer_early_get_count();
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return lldiv(ticks * 1000, timer_early_get_rate());
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}
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/* DM timer functions */
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static uint64_t dm_orion_timer_get_count(struct udevice *dev)
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{
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struct orion_timer_priv *priv = dev_get_priv(dev);
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return orion_timer_get_count(priv->base);
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}
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static int orion_timer_probe(struct udevice *dev)
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{
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struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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enum input_clock_type type = dev_get_driver_data(dev);
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struct orion_timer_priv *priv = dev_get_priv(dev);
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priv->base = devfdt_remap_addr_index(dev, 0);
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if (!priv->base) {
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debug("unable to map registers\n");
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return -ENOMEM;
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}
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if (type == INPUT_CLOCK_25MHZ)
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uc_priv->clock_rate = MVEBU_TIMER_FIXED_RATE_25MHZ;
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else
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uc_priv->clock_rate = CFG_SYS_TCLK;
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orion_timer_init(priv->base, type);
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return 0;
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}
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static const struct timer_ops orion_timer_ops = {
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.get_count = dm_orion_timer_get_count,
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};
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static const struct udevice_id orion_timer_ids[] = {
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{ .compatible = "marvell,orion-timer", .data = INPUT_CLOCK_NON_FIXED },
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{ .compatible = "marvell,armada-370-timer", .data = INPUT_CLOCK_25MHZ },
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{ .compatible = "marvell,armada-xp-timer", .data = INPUT_CLOCK_25MHZ },
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{}
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};
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U_BOOT_DRIVER(orion_timer) = {
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.name = "orion_timer",
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.id = UCLASS_TIMER,
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.of_match = orion_timer_ids,
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.probe = orion_timer_probe,
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.ops = &orion_timer_ops,
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.priv_auto = sizeof(struct orion_timer_priv),
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};
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