3b74e7ec58
Move needed definitions (register descriptions etc.) from include/mpc512x.h into include/asm-ppc/immap_512x.h. Instead of using a #define'd register offset, use a function that provides the PATA controller's base address. All the rest of include/mpc512x.h are register offset definitions which can be eliminated by proper use of C structures. There are only a few register offsets remaining that are needed in cpu/mpc512x/start.S; for these we provide cpu/mpc512x/asm-offsets.h which is intended as a temporary workaround only. In a later patch this file will be removed, too, and then auto-generated from the respective C structs. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: John Rigby <jcrigby@gmail.com>
99 lines
3.2 KiB
C
99 lines
3.2 KiB
C
/*
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* (C) Copyright 2003 - 2009
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* Derived from the MPC8xx driver's header file.
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*/
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#ifndef __MPC512X_FEC_H
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#define __MPC512X_FEC_H
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#include <common.h>
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/* Receive & Transmit Buffer Descriptor definitions */
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typedef struct BufferDescriptor {
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u16 status;
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u16 dataLength;
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u32 dataPointer;
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} FEC_RBD;
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typedef struct {
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u16 status;
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u16 dataLength;
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u32 dataPointer;
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} FEC_TBD;
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/* private structure */
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typedef enum {
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SEVENWIRE, /* 7-wire */
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MII10, /* MII 10Mbps */
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MII100 /* MII 100Mbps */
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} xceiver_type;
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/* BD Numer definitions */
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#define FEC_TBD_NUM 48 /* The user can adjust this value */
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#define FEC_RBD_NUM 32 /* The user can adjust this value */
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/* packet size limit */
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#define FEC_MAX_FRAME_LEN 1522 /* recommended default value */
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/* Buffer size must be evenly divisible by 16 */
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#define FEC_BUFFER_SIZE ((FEC_MAX_FRAME_LEN + 0x10) & (~0xf))
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typedef struct {
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u8 frame[FEC_BUFFER_SIZE];
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} mpc512x_frame;
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typedef struct {
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FEC_RBD rbd[FEC_RBD_NUM]; /* RBD ring */
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FEC_TBD tbd[FEC_TBD_NUM]; /* TBD ring */
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mpc512x_frame recv_frames[FEC_RBD_NUM]; /* receive buff */
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} mpc512x_buff_descs;
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typedef struct {
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volatile fec512x_t *eth;
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xceiver_type xcv_type; /* transceiver type */
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mpc512x_buff_descs *bdBase; /* BD rings and recv buffer */
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u16 rbdIndex; /* next receive BD to read */
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u16 tbdIndex; /* next transmit BD to send */
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u16 usedTbdIndex; /* next transmit BD to clean */
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u16 cleanTbdNum; /* the number of available transmit BDs */
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} mpc512x_fec_priv;
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/* RBD bits definitions */
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#define FEC_RBD_EMPTY 0x8000 /* Buffer is empty */
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#define FEC_RBD_WRAP 0x2000 /* Last BD in ring */
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#define FEC_RBD_LAST 0x0800 /* Buffer is last in frame(useless) */
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#define FEC_RBD_MISS 0x0100 /* Miss bit for prom mode */
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#define FEC_RBD_BC 0x0080 /* The received frame is broadcast frame */
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#define FEC_RBD_MC 0x0040 /* The received frame is multicast frame */
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#define FEC_RBD_LG 0x0020 /* Frame length violation */
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#define FEC_RBD_NO 0x0010 /* Nonoctet align frame */
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#define FEC_RBD_SH 0x0008 /* Short frame */
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#define FEC_RBD_CR 0x0004 /* CRC error */
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#define FEC_RBD_OV 0x0002 /* Receive FIFO overrun */
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#define FEC_RBD_TR 0x0001 /* Frame is truncated */
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#define FEC_RBD_ERR (FEC_RBD_LG | FEC_RBD_NO | FEC_RBD_CR | \
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FEC_RBD_OV | FEC_RBD_TR)
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/* TBD bits definitions */
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#define FEC_TBD_READY 0x8000 /* Buffer is ready */
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#define FEC_TBD_WRAP 0x2000 /* Last BD in ring */
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#define FEC_TBD_LAST 0x0800 /* Buffer is last in frame */
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#define FEC_TBD_TC 0x0400 /* Transmit the CRC */
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#define FEC_TBD_ABC 0x0200 /* Append bad CRC */
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/* MII-related definitios */
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#define FEC_MII_DATA_ST 0x40000000 /* Start of frame delimiter */
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#define FEC_MII_DATA_OP_RD 0x20000000 /* Perform a read operation */
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#define FEC_MII_DATA_OP_WR 0x10000000 /* Perform a write operation */
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#define FEC_MII_DATA_PA_MSK 0x0f800000 /* PHY Address field mask */
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#define FEC_MII_DATA_RA_MSK 0x007c0000 /* PHY Register field mask */
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#define FEC_MII_DATA_TA 0x00020000 /* Turnaround */
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#define FEC_MII_DATA_DATAMSK 0x0000ffff /* PHY data field */
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#define FEC_MII_DATA_RA_SHIFT 18 /* MII Register address bits */
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#define FEC_MII_DATA_PA_SHIFT 23 /* MII PHY address bits */
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#endif /* __MPC512X_FEC_H */
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