401d1c4f5d
Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
135 lines
3.2 KiB
C
135 lines
3.2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Qualcomm GPIO driver
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*
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* (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <asm/global_data.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* Register offsets */
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#define GPIO_CONFIG_OFF(no) ((no) * 0x1000)
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#define GPIO_IN_OUT_OFF(no) ((no) * 0x1000 + 0x4)
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/* OE */
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#define GPIO_OE_DISABLE (0x0 << 9)
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#define GPIO_OE_ENABLE (0x1 << 9)
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#define GPIO_OE_MASK (0x1 << 9)
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/* GPIO_IN_OUT register shifts. */
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#define GPIO_IN 0
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#define GPIO_OUT 1
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struct msm_gpio_bank {
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phys_addr_t base;
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};
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static int msm_gpio_direction_input(struct udevice *dev, unsigned int gpio)
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{
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struct msm_gpio_bank *priv = dev_get_priv(dev);
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phys_addr_t reg = priv->base + GPIO_CONFIG_OFF(gpio);
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/* Disable OE bit */
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clrsetbits_le32(reg, GPIO_OE_MASK, GPIO_OE_DISABLE);
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return 0;
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}
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static int msm_gpio_set_value(struct udevice *dev, unsigned gpio, int value)
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{
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struct msm_gpio_bank *priv = dev_get_priv(dev);
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value = !!value;
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/* set value */
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writel(value << GPIO_OUT, priv->base + GPIO_IN_OUT_OFF(gpio));
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return 0;
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}
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static int msm_gpio_direction_output(struct udevice *dev, unsigned gpio,
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int value)
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{
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struct msm_gpio_bank *priv = dev_get_priv(dev);
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phys_addr_t reg = priv->base + GPIO_CONFIG_OFF(gpio);
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value = !!value;
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/* set value */
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writel(value << GPIO_OUT, priv->base + GPIO_IN_OUT_OFF(gpio));
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/* switch direction */
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clrsetbits_le32(reg, GPIO_OE_MASK, GPIO_OE_ENABLE);
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return 0;
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}
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static int msm_gpio_get_value(struct udevice *dev, unsigned gpio)
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{
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struct msm_gpio_bank *priv = dev_get_priv(dev);
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return !!(readl(priv->base + GPIO_IN_OUT_OFF(gpio)) >> GPIO_IN);
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}
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static int msm_gpio_get_function(struct udevice *dev, unsigned offset)
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{
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struct msm_gpio_bank *priv = dev_get_priv(dev);
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if (readl(priv->base + GPIO_CONFIG_OFF(offset)) & GPIO_OE_ENABLE)
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return GPIOF_OUTPUT;
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return GPIOF_INPUT;
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}
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static const struct dm_gpio_ops gpio_msm_ops = {
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.direction_input = msm_gpio_direction_input,
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.direction_output = msm_gpio_direction_output,
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.get_value = msm_gpio_get_value,
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.set_value = msm_gpio_set_value,
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.get_function = msm_gpio_get_function,
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};
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static int msm_gpio_probe(struct udevice *dev)
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{
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struct msm_gpio_bank *priv = dev_get_priv(dev);
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priv->base = dev_read_addr(dev);
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return priv->base == FDT_ADDR_T_NONE ? -EINVAL : 0;
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}
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static int msm_gpio_of_to_plat(struct udevice *dev)
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{
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struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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uc_priv->gpio_count = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
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"gpio-count", 0);
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uc_priv->bank_name = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
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"gpio-bank-name", NULL);
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if (uc_priv->bank_name == NULL)
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uc_priv->bank_name = "soc";
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return 0;
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}
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static const struct udevice_id msm_gpio_ids[] = {
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{ .compatible = "qcom,msm8916-pinctrl" },
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{ .compatible = "qcom,apq8016-pinctrl" },
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{ .compatible = "qcom,ipq4019-pinctrl" },
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{ }
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};
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U_BOOT_DRIVER(gpio_msm) = {
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.name = "gpio_msm",
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.id = UCLASS_GPIO,
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.of_match = msm_gpio_ids,
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.of_to_plat = msm_gpio_of_to_plat,
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.probe = msm_gpio_probe,
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.ops = &gpio_msm_ops,
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.priv_auto = sizeof(struct msm_gpio_bank),
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};
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