6b24501438
Add PL bitstream dowload support for ZynqMP Bitstream will be validated by uboot and loaded to PL by invoking an smc instruction to ATF which route this request to PMU FW which will take care of loading it to PL Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
52 lines
1.2 KiB
Plaintext
52 lines
1.2 KiB
Plaintext
CONFIG_ARM=y
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CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm018_dc4"
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CONFIG_ARCH_ZYNQMP=y
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CONFIG_SYS_MALLOC_F_LEN=0x8000
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CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1751 xm018 dc4"
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CONFIG_SYS_TEXT_BASE=0x8000000
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CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm018-dc4"
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CONFIG_FIT=y
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CONFIG_FIT_VERBOSE=y
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CONFIG_SPL_LOAD_FIT=y
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CONFIG_SPL=y
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CONFIG_SPL_SYS_MALLOC_SIMPLE=y
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CONFIG_HUSH_PARSER=y
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CONFIG_SYS_PROMPT="ZynqMP> "
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# CONFIG_CMD_IMLS is not set
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CONFIG_CMD_MEMTEST=y
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# CONFIG_CMD_FLASH is not set
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CONFIG_CMD_MMC=y
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CONFIG_CMD_I2C=y
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CONFIG_CMD_TFTPPUT=y
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CONFIG_CMD_DHCP=y
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CONFIG_CMD_MII=y
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CONFIG_CMD_PING=y
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CONFIG_CMD_TIME=y
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CONFIG_CMD_TIMER=y
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CONFIG_CMD_EXT2=y
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CONFIG_CMD_EXT4=y
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CONFIG_CMD_EXT4_WRITE=y
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CONFIG_CMD_FAT=y
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CONFIG_CMD_FS_GENERIC=y
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CONFIG_SPL_OF_CONTROL=y
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CONFIG_OF_EMBED=y
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CONFIG_NET_RANDOM_ETHADDR=y
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CONFIG_SPL_DM=y
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CONFIG_SPL_DM_SEQ_ALIAS=y
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CONFIG_BLK=y
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CONFIG_FPGA_XILINX=y
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CONFIG_FPGA_ZYNQMPPL=y
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CONFIG_DM_GPIO=y
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CONFIG_DM_I2C=y
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CONFIG_SYS_I2C_CADENCE=y
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CONFIG_DM_MMC=y
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CONFIG_DM_MMC_OPS=y
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CONFIG_ZYNQ_SDHCI=y
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CONFIG_DM_ETH=y
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CONFIG_ZYNQ_GEM=y
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CONFIG_DEBUG_UART=y
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CONFIG_DEBUG_UART_ZYNQ=y
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CONFIG_DEBUG_UART_BASE=0xff000000
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CONFIG_DEBUG_UART_CLOCK=100000000
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CONFIG_DEBUG_UART_ANNOUNCE=y
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