699b13a606
seconds instead of ms. * Patch by Robert Schwebel, 1 Nov 2002: XScale related cleanup (affects all ARM boards) * Cleanup of names, warnings and README.
215 lines
6.7 KiB
C
215 lines
6.7 KiB
C
/*
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* (C) Copyright 2000, 2001, 2002
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* Robert Schwebel, Pengutronix, r.schwebel@pengutronix.de.
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*
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* Configuration for the Cogent CSB226 board. For details see
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* http://www.cogcomp.com/csb_csb226.htm
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* include/configs/csb226.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define DEBUG 1
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/*
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* If we are developing, we might want to start U-Boot from ram
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* so we MUST NOT initialize critical regs like mem-timing ...
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*/
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#define CONFIG_INIT_CRITICAL /* undef for developing */
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_PXA250 1 /* This is an PXA250 CPU */
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#define CONFIG_CSB226 1 /* on a CSB226 board */
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#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
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/* for timer/console/ethernet */
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/*
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* Hardware drivers
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*/
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/*
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* select serial console configuration
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*/
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#define CONFIG_FFUART 1 /* we use FFUART on CSB226 */
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_BAUDRATE 19200
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#define CONFIG_COMMANDS (CONFIG_CMD_DFL & ~CFG_CMD_NET)
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#include <cmd_confdefs.h>
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#define CONFIG_BOOTDELAY 3
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#define CONFIG_BOOTARGS "root=/dev/nfs ip=bootp console=ttyS0,19200"
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#define CONFIG_ETHADDR FF:FF:FF:FF:FF:FF
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#define CONFIG_NETMASK 255.255.255.0
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#define CONFIG_IPADDR 192.168.1.56
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#define CONFIG_SERVERIP 192.168.1.2
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#define CONFIG_BOOTCOMMAND "bootm 0x40000"
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
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#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
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#endif
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/*
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* Miscellaneous configurable options
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*/
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/*
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* Size of malloc() pool; this lives below the uppermost 128 KiB which are
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* used for the RAM copy of the uboot code
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*
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*/
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#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "uboot> " /* Monitor Command Prompt */
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#define CFG_CBSIZE 128 /* Console I/O Buffer Size */
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */
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#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
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#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
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#define CFG_LOAD_ADDR 0xa7fe0000 /* default load address */
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/* RS: where is this documented? */
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/* RS: is this where U-Boot is */
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/* RS: relocated to in RAM? */
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#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
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/* RS: the oscillator is actually 3680130?? */
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#define CFG_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */
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/* 0101000001 */
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/* ^^^^^ Memory Speed 99.53 MHz */
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/* ^^ Run Mode Speed = 2x Mem Speed */
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/* ^^ Turbo Mode Sp. = 1x Run M. Sp. */
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#define CFG_MONITOR_LEN 0x20000 /* 128 KiB */
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/* valid baudrates */
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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/*
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* Stack sizes
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*
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* The stack sizes are set up in start.S using the settings below
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*/
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#define CONFIG_STACKSIZE (128*1024) /* regular stack */
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#ifdef CONFIG_USE_IRQ
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#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
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#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
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#endif
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/*
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* Physical Memory Map
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*/
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#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
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#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
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#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
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#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
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#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
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#define CFG_DRAM_BASE 0xa0000000 /* RAM starts here */
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#define CFG_DRAM_SIZE 0x02000000
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#define CFG_FLASH_BASE PHYS_FLASH_1
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/*
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* GPIO settings
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*/
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#define CFG_GPSR0_VAL 0xFFFFFFFF
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#define CFG_GPSR1_VAL 0xFFFFFFFF
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#define CFG_GPSR2_VAL 0xFFFFFFFF
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#define CFG_GPCR0_VAL 0x08022080
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#define CFG_GPCR1_VAL 0x00000000
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#define CFG_GPCR2_VAL 0x00000000
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#define CFG_GPDR0_VAL 0xCD82A858
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#define CFG_GPDR1_VAL 0xFCFFAB80
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#define CFG_GPDR2_VAL 0x0001FFFF
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#define CFG_GAFR0_L_VAL 0x80000000
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#define CFG_GAFR0_U_VAL 0xA5254010
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#define CFG_GAFR1_L_VAL 0x599A9550
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#define CFG_GAFR1_U_VAL 0xAAA5AAAA
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#define CFG_GAFR2_L_VAL 0xAAAAAAAA
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#define CFG_GAFR2_U_VAL 0x00000002
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/* FIXME: set GPIO_RER/FER */
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#define CFG_PSSR_VAL 0x20
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/*
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* Memory settings
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*/
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#define CFG_MSC0_VAL 0x2EF025D0
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#define CFG_MSC1_VAL 0x00003F64
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#define CFG_MSC2_VAL 0x00000000
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#define CFG_MDCNFG_VAL 0x09a909a9
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#define CFG_MDREFR_VAL 0x03ca0030
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#define CFG_MDMRS_VAL 0x00220022
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/*
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* PCMCIA and CF Interfaces
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*/
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#define CFG_MECR_VAL 0x00000000
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#define CFG_MCMEM0_VAL 0x00000000
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#define CFG_MCMEM1_VAL 0x00000000
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#define CFG_MCATT0_VAL 0x00000000
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#define CFG_MCATT1_VAL 0x00000000
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#define CFG_MCIO0_VAL 0x00000000
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#define CFG_MCIO1_VAL 0x00000000
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/*
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#define _LED 0x08000010
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#define LED_BLANK (0x08000040)
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*/
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/*
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* FLASH and environment organization
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*/
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#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT 128 /* max number of sect. on one chip */
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/* timeout values are in ticks */
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#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */
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#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */
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#define CFG_ENV_IS_IN_FLASH 1
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#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x1C000)
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/* Addr of Environment Sector */
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#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
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#endif /* __CONFIG_H */
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