69245e406e
This function is empty, drop it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Cc: Sean Anderson <seanga2@gmail.com> Cc: Simon Glass <sjg@chromium.org> Cc: Steven Lawrance <steven.lawrance@softathome.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
150 lines
2.9 KiB
C
150 lines
2.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* K+P iMX6Q KP_IMX6Q_TPC board configuration
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*
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* Copyright (C) 2018 Lukasz Majewski <lukma@denx.de>
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*/
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#include <common.h>
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#include <init.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/mx6-pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/global_data.h>
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#include <asm/mach-imx/boot_mode.h>
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#include <env.h>
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#include <errno.h>
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#include <miiphy.h>
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#include <usb.h>
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#include <usb/ehci-ci.h>
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#include <led.h>
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DECLARE_GLOBAL_DATA_PTR;
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int dram_init(void)
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{
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gd->ram_size = imx_ddr_size();
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return 0;
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}
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/*
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* Do not overwrite the console
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* Use always serial for U-Boot console
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*/
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int overwrite_console(void)
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{
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return 1;
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}
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#ifdef CONFIG_FEC_MXC
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static int setup_fec_clock(void)
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{
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struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
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/* set gpr1[21] to select anatop clock */
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clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK,
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IOMUXC_GPR1_ENET_CLK_SEL_MASK);
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return enable_fec_anatop_clock(0, ENET_50MHZ);
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}
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static int ar8031_phy_fixup(struct phy_device *phydev)
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{
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unsigned short val;
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/* To enable AR8031 output a 125MHz clk from CLK_25M */
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phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
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phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
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phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
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val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
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val &= 0xffe3;
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val |= 0x18;
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phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
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/* introduce tx clock delay */
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
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val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
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val |= 0x0100;
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
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return 0;
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}
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int board_phy_config(struct phy_device *phydev)
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{
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ar8031_phy_fixup(phydev);
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if (phydev->drv->config)
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phydev->drv->config(phydev);
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return 0;
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}
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#endif
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#ifdef CONFIG_USB_EHCI_MX6
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static void setup_usb(void)
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{
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/*
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* Set daisy chain for otg_pin_id on MX6Q.
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* For MX6DL, this bit is reserved.
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*/
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imx_iomux_set_gpr_register(1, 13, 1, 0);
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}
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#endif
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int board_early_init_f(void)
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{
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#ifdef CONFIG_USB_EHCI_MX6
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setup_usb();
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#endif
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#ifdef CONFIG_FEC_MXC
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setup_fec_clock();
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#endif
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return 0;
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}
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int board_init(void)
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{
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struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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/* address of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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/* Enable eim_slow clocks */
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setbits_le32(&mxc_ccm->CCGR6, 0x1 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET);
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return 0;
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}
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#ifdef CONFIG_CMD_BMODE
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static const struct boot_mode board_boot_modes[] = {
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/* 4 bit bus width */
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{"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
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/* 8 bit bus width */
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{"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
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{NULL, 0},
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};
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#endif
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int board_late_init(void)
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{
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#ifdef CONFIG_CMD_BMODE
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add_board_boot_modes(board_boot_modes);
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#endif
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env_set("boardname", "kp-tpc");
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env_set("boardsoc", "imx6q");
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return 0;
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}
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int checkboard(void)
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{
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puts("Board: K+P KP_IMX6Q_TPC i.MX6Q\n");
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return 0;
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}
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