493 lines
16 KiB
C
493 lines
16 KiB
C
/*
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* (C) Copyright 2001-2005
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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*
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* Configuration settings for the CPC45 board.
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*
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*/
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/* ------------------------------------------------------------------------- */
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_MPC824X 1
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#define CONFIG_MPC8245 1
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#define CONFIG_CPC45 1
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#define CONFIG_SYS_TEXT_BASE 0xFFF00000
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_BAUDRATE 9600
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#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
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#define CONFIG_BOOTDELAY 5
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_SUBNETMASK
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_BOOTFILESIZE
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_BEDBUG
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_EEPROM
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#define CONFIG_CMD_EXT2
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_FLASH
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_IDE
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#define CONFIG_CMD_NFS
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_SDRAM
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#define CONFIG_CMD_SNTP
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#if 1
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#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */
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#endif
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/* Print Buffer Size
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*/
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
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*/
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#if defined(CONFIG_BOOT_ROM)
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#define CONFIG_SYS_FLASH_BASE 0xFF000000
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#else
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#define CONFIG_SYS_FLASH_BASE 0xFF800000
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#endif
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#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
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#define CONFIG_SYS_EUMB_ADDR 0xFCE00000
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
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#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
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#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
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/* Maximum amount of RAM.
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*/
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#define CONFIG_SYS_MAX_RAM_SIZE 0x10000000
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#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
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#undef CONFIG_SYS_RAMBOOT
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#else
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#define CONFIG_SYS_RAMBOOT
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#endif
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area
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*/
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#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
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#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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/*
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* NS16550 Configuration
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*/
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_EUMB_ADDR + 0x4500)
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_EUMB_ADDR + 0x4600)
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#define DUART_DCR (CONFIG_SYS_EUMB_ADDR + 0x4511)
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/*
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* I2C configuration
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*/
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#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
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#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
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#define CONFIG_SYS_I2C_SLAVE 0x7F
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/*
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* RTC configuration
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*/
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#define CONFIG_RTC_PCF8563
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#define CONFIG_SYS_I2C_RTC_ADDR 0x51
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/*
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* EEPROM configuration
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*/
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
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#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
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/*
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* Low Level Configuration Settings
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* (address mappings, register initial values, etc.)
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* You should know what you are doing if you make changes here.
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* For the detail description refer to the MPC8240 user's manual.
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*/
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#define CONFIG_SYS_CLK_FREQ 33000000
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#define CONFIG_SYS_HZ 1000
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/* Bit-field values for MCCR1.
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*/
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#define CONFIG_SYS_ROMNAL 0
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#define CONFIG_SYS_ROMFAL 8
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#define CONFIG_SYS_BANK0_ROW 0 /* SDRAM bank 7-0 row address */
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#define CONFIG_SYS_BANK1_ROW 0
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#define CONFIG_SYS_BANK2_ROW 0
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#define CONFIG_SYS_BANK3_ROW 0
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#define CONFIG_SYS_BANK4_ROW 0
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#define CONFIG_SYS_BANK5_ROW 0
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#define CONFIG_SYS_BANK6_ROW 0
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#define CONFIG_SYS_BANK7_ROW 0
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/* Bit-field values for MCCR2.
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*/
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#define CONFIG_SYS_REFINT 0x2ec
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/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
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*/
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#define CONFIG_SYS_BSTOPRE 160
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/* Bit-field values for MCCR3.
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*/
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#define CONFIG_SYS_REFREC 2 /* Refresh to activate interval */
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#define CONFIG_SYS_RDLAT 0 /* Data latancy from read command */
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/* Bit-field values for MCCR4.
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*/
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#define CONFIG_SYS_PRETOACT 2 /* Precharge to activate interval */
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#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */
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#define CONFIG_SYS_SDMODE_CAS_LAT 2 /* SDMODE CAS latancy */
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#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */
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#define CONFIG_SYS_SDMODE_BURSTLEN 2 /* SDMODE Burst length */
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#define CONFIG_SYS_ACTORW 2
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#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
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#define CONFIG_SYS_EXTROM 0
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#define CONFIG_SYS_REGDIMM 0
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/* Memory bank settings.
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* Only bits 20-29 are actually used from these vales to set the
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* start/end addresses. The upper two bits will always be 0, and the lower
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* 20 bits will be 0x00000 for a start address, or 0xfffff for an end
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* address. Refer to the MPC8240 book.
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*/
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#define CONFIG_SYS_BANK0_START 0x00000000
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#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1)
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#define CONFIG_SYS_BANK0_ENABLE 1
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#define CONFIG_SYS_BANK1_START 0x3ff00000
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#define CONFIG_SYS_BANK1_END 0x3fffffff
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#define CONFIG_SYS_BANK1_ENABLE 0
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#define CONFIG_SYS_BANK2_START 0x3ff00000
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#define CONFIG_SYS_BANK2_END 0x3fffffff
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#define CONFIG_SYS_BANK2_ENABLE 0
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#define CONFIG_SYS_BANK3_START 0x3ff00000
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#define CONFIG_SYS_BANK3_END 0x3fffffff
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#define CONFIG_SYS_BANK3_ENABLE 0
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#define CONFIG_SYS_BANK4_START 0x3ff00000
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#define CONFIG_SYS_BANK4_END 0x3fffffff
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#define CONFIG_SYS_BANK4_ENABLE 0
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#define CONFIG_SYS_BANK5_START 0x3ff00000
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#define CONFIG_SYS_BANK5_END 0x3fffffff
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#define CONFIG_SYS_BANK5_ENABLE 0
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#define CONFIG_SYS_BANK6_START 0x3ff00000
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#define CONFIG_SYS_BANK6_END 0x3fffffff
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#define CONFIG_SYS_BANK6_ENABLE 0
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#define CONFIG_SYS_BANK7_START 0x3ff00000
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#define CONFIG_SYS_BANK7_END 0x3fffffff
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#define CONFIG_SYS_BANK7_ENABLE 0
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#define CONFIG_SYS_ODCR 0xff
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#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */
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/* currently accessed page in memory */
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/* see 8240 book for details */
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#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
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#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
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#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_IBAT3L (0xFC000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
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#define CONFIG_SYS_IBAT3U (0xFC000000 | BATU_BL_64M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
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#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
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#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
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#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
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#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
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#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
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#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
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#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 39 /* Max number of sectors in one bank */
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#define INTEL_ID_28F160F3T 0x88F388F3 /* 16M = 1M x 16 top boot sector */
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#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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/* Warining: environment is not EMBEDDED in the ppcboot code.
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* It's stored in flash separately.
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*/
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x7F8000)
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#define CONFIG_ENV_SIZE 0x4000 /* Size of the Environment */
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#define CONFIG_ENV_OFFSET 0 /* starting right at the beginning */
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#define CONFIG_ENV_SECT_SIZE 0x8000 /* Size of the Environment Sector */
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CONFIG_SYS_CACHELINE_SIZE 32
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#if defined(CONFIG_CMD_KGDB)
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# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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#endif
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/*----------------------------------------------------------------------*/
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/* CPC45 Memory Map */
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/*----------------------------------------------------------------------*/
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#define SRAM_BASE 0x80000000 /* SRAM base address */
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#define SRAM_END 0x801FFFFF
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#define ST16552_A_BASE 0x80200000 /* ST16552 channel A */
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#define ST16552_B_BASE 0x80400000 /* ST16552 channel A */
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#define BCSR_BASE 0x80600000 /* board control / status registers */
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#define DISPLAY_BASE 0x80600040 /* DISPLAY base */
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#define PCMCIA_MEM_BASE 0x83000000 /* PCMCIA memory window base */
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#define PCMCIA_IO_BASE 0xFE000000 /* PCMCIA IO window base */
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#define CONFIG_SYS_SRAM_BASE SRAM_BASE
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#define CONFIG_SYS_SRAM_SIZE (SRAM_END - SRAM_BASE + 1)
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/*---------------------------------------------------------------------*/
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/* CPC45 Control/Status Registers */
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/*---------------------------------------------------------------------*/
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#define IRQ_ENA_1 *((volatile uchar*)(BCSR_BASE + 0x00))
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#define IRQ_STAT_1 *((volatile uchar*)(BCSR_BASE + 0x01))
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#define IRQ_ENA_2 *((volatile uchar*)(BCSR_BASE + 0x02))
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#define IRQ_STAT_2 *((volatile uchar*)(BCSR_BASE + 0x03))
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#define BOARD_CTRL *((volatile uchar*)(BCSR_BASE + 0x04))
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#define BOARD_STAT *((volatile uchar*)(BCSR_BASE + 0x05))
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#define WDG_START *((volatile uchar*)(BCSR_BASE + 0x06))
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#define WDG_PRESTOP *((volatile uchar*)(BCSR_BASE + 0x06))
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#define WDG_STOP *((volatile uchar*)(BCSR_BASE + 0x06))
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#define BOARD_REV *((volatile uchar*)(BCSR_BASE + 0x07))
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/* IRQ_ENA_1 bit definitions */
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#define I_ENA_1_IERA 0x80 /* INTA enable */
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#define I_ENA_1_IERB 0x40 /* INTB enable */
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#define I_ENA_1_IERC 0x20 /* INTC enable */
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#define I_ENA_1_IERD 0x10 /* INTD enable */
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/* IRQ_STAT_1 bit definitions */
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#define I_STAT_1_INTA 0x80 /* INTA status */
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#define I_STAT_1_INTB 0x40 /* INTB status */
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#define I_STAT_1_INTC 0x20 /* INTC status */
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#define I_STAT_1_INTD 0x10 /* INTD status */
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/* IRQ_ENA_2 bit definitions */
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#define I_ENA_2_IEAB 0x80 /* ABORT IRQ enable */
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#define I_ENA_2_IEK1 0x40 /* KEY1 IRQ enable */
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#define I_ENA_2_IEK2 0x20 /* KEY2 IRQ enable */
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#define I_ENA_2_IERT 0x10 /* RTC IRQ enable */
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#define I_ENA_2_IESM 0x08 /* LM81 IRQ enable */
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#define I_ENA_2_IEDG 0x04 /* DEGENERATING IRQ enable */
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#define I_ENA_2_IES2 0x02 /* ST16552/B IRQ enable */
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#define I_ENA_2_IES1 0x01 /* ST16552/A IRQ enable */
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/* IRQ_STAT_2 bit definitions */
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#define I_STAT_2_ABO 0x80 /* ABORT IRQ status */
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#define I_STAT_2_KY1 0x40 /* KEY1 IRQ status */
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#define I_STAT_2_KY2 0x20 /* KEY2 IRQ status */
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#define I_STAT_2_RTC 0x10 /* RTC IRQ status */
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#define I_STAT_2_SMN 0x08 /* LM81 IRQ status */
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#define I_STAT_2_DEG 0x04 /* DEGENERATING IRQ status */
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#define I_STAT_2_SIO2 0x02 /* ST16552/B IRQ status */
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#define I_STAT_2_SIO1 0x01 /* ST16552/A IRQ status */
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/* BOARD_CTRL bit definitions */
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#define USER_LEDS 2 /* 2 user LEDs */
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#if (USER_LEDS == 4)
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#define B_CTRL_WRSE 0x80
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#define B_CTRL_KRSE 0x40
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#define B_CTRL_FWRE 0x20 /* Flash write enable */
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#define B_CTRL_FWPT 0x10 /* Flash write protect */
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#define B_CTRL_LED3 0x08 /* LED 3 control */
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#define B_CTRL_LED2 0x04 /* LED 2 control */
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#define B_CTRL_LED1 0x02 /* LED 1 control */
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#define B_CTRL_LED0 0x01 /* LED 0 control */
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#else
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#define B_CTRL_WRSE 0x80
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#define B_CTRL_KRSE 0x40
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#define B_CTRL_FWRE_1 0x20 /* Flash write enable */
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#define B_CTRL_FWPT_1 0x10 /* Flash write protect */
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#define B_CTRL_LED1 0x08 /* LED 1 control */
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#define B_CTRL_LED0 0x04 /* LED 0 control */
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#define B_CTRL_FWRE_0 0x02 /* Flash write enable */
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#define B_CTRL_FWPT_0 0x01 /* Flash write protect */
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#endif
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/* BOARD_STAT bit definitions */
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#define B_STAT_WDGE 0x80
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#define B_STAT_WDGS 0x40
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#define B_STAT_WRST 0x20
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#define B_STAT_KRST 0x10
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#define B_STAT_CSW3 0x08 /* sitch bit 3 status */
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#define B_STAT_CSW2 0x04 /* sitch bit 2 status */
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#define B_STAT_CSW1 0x02 /* sitch bit 1 status */
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#define B_STAT_CSW0 0x01 /* sitch bit 0 status */
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/*---------------------------------------------------------------------*/
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/* Display addresses */
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/*---------------------------------------------------------------------*/
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#define DISP_UDC_RAM (DISPLAY_BASE + 0x08) /* UDC RAM */
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#define DISP_CHR_RAM (DISPLAY_BASE + 0x18) /* character Ram */
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#define DISP_FLASH (DISPLAY_BASE + 0x20) /* Flash Ram */
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#define DISP_UDC_ADR *((volatile uchar*)(DISPLAY_BASE + 0x00)) /* UDC Address Reg. */
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#define DISP_CWORD *((volatile uchar*)(DISPLAY_BASE + 0x10)) /* Control Word Reg. */
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#define DISP_DIG0 *((volatile uchar*)(DISP_CHR_RAM + 0x00)) /* Digit 0 address */
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#define DISP_DIG1 *((volatile uchar*)(DISP_CHR_RAM + 0x01)) /* Digit 0 address */
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#define DISP_DIG2 *((volatile uchar*)(DISP_CHR_RAM + 0x02)) /* Digit 0 address */
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#define DISP_DIG3 *((volatile uchar*)(DISP_CHR_RAM + 0x03)) /* Digit 0 address */
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#define DISP_DIG4 *((volatile uchar*)(DISP_CHR_RAM + 0x04)) /* Digit 0 address */
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#define DISP_DIG5 *((volatile uchar*)(DISP_CHR_RAM + 0x05)) /* Digit 0 address */
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#define DISP_DIG6 *((volatile uchar*)(DISP_CHR_RAM + 0x06)) /* Digit 0 address */
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#define DISP_DIG7 *((volatile uchar*)(DISP_CHR_RAM + 0x07)) /* Digit 0 address */
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/*-----------------------------------------------------------------------
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* PCI stuff
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*-----------------------------------------------------------------------
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*/
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#define CONFIG_PCI /* include pci support */
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#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
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#define CONFIG_SYS_EARLY_PCI_INIT
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#undef CONFIG_PCI_PNP
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#undef CONFIG_PCI_SCAN_SHOW
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#define CONFIG_EEPRO100
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#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
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#define PCI_ENET0_IOADDR 0x82000000
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#define PCI_ENET0_MEMADDR 0x82000000
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#define PCI_PLX9030_IOADDR 0x82100000
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#define PCI_PLX9030_MEMADDR 0x82100000
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/*-----------------------------------------------------------------------
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* PCMCIA stuff
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*-----------------------------------------------------------------------
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*/
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#define CONFIG_I82365
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#define CONFIG_SYS_PCMCIA_MEM_ADDR PCMCIA_MEM_BASE
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#define CONFIG_SYS_PCMCIA_MEM_SIZE 0x1000
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#define CONFIG_PCMCIA_SLOT_A
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/*-----------------------------------------------------------------------
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* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
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*-----------------------------------------------------------------------
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*/
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#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
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#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
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#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
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#undef CONFIG_IDE_RESET /* reset for IDE not supported */
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#define CONFIG_IDE_LED /* LED for IDE is supported */
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#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
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#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
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#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
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#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
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#define CONFIG_SYS_ATA_DATA_OFFSET CONFIG_SYS_PCMCIA_MEM_SIZE
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/* Offset for normal register accesses */
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#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
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/* Offset for alternate registers */
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#define CONFIG_SYS_ATA_ALT_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x400)
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#define CONFIG_DOS_PARTITION
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#endif /* __CONFIG_H */
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