4fa4267d82
Add a v5l2 cache controller driver that is usually found on Andes RISC-V ae350 platform. It will parse the cache settings from the dtb. In this version tag and data ram control timing can be adjusted by the requirement from the dtb. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
35 lines
917 B
Plaintext
35 lines
917 B
Plaintext
#
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# Cache controllers
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#
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menu "Cache Controller drivers"
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config CACHE
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bool "Enable Driver Model for Cache controllers"
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depends on DM
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help
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Enable driver model for cache controllers that are found on
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most CPU's. Cache is memory that the CPU can access directly and
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is usually located on the same chip. This uclass can be used for
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configuring settings that be found from a device tree file.
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config L2X0_CACHE
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tristate "PL310 cache driver"
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select CACHE
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depends on ARM
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help
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This driver is for the PL310 cache controller commonly found on
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ARMv7(32-bit) devices. The driver configures the cache settings
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found in the device tree.
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config V5L2_CACHE
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bool "Andes V5L2 cache driver"
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select CACHE
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depends on RISCV_NDS_CACHE
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help
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Support Andes V5L2 cache controller in AE350 platform.
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It will configure tag and data ram timing control from the
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device tree and enable L2 cache.
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endmenu
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