1a4596601f
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
148 lines
4.5 KiB
C
148 lines
4.5 KiB
C
/*
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* Copyright (c) 2004 Picture Elements, Inc.
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* Stephen Williams (steve@icarus.com)
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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# include <common.h>
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# include <asm/ppc4xx.h>
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# include <asm/processor.h>
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# include <asm/io.h>
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# include "jse_priv.h"
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/*
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* This function is run very early, out of flash, and before devices are
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* initialized. It is called by arch/powerpc/lib/board.c:board_init_f by virtue
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* of being in the init_sequence array.
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*
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* The SDRAM has been initialized already -- start.S:start called
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* init.S:init_sdram early on -- but it is not yet being used for
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* anything, not even stack. So be careful.
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*/
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int board_early_init_f (void)
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{
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/*-------------------------------------------------------------------------+
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| Interrupt controller setup for the JSE board.
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| Note: IRQ 0-15 405GP internally generated; active high; level sensitive
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| IRQ 16 405GP internally generated; active low; level sensitive
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| IRQ 17-24 RESERVED/UNUSED
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| IRQ 25 (EXT IRQ 0) PCI SLOT 0; active low; level sensitive
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| IRQ 26 (EXT IRQ 1) PCI SLOT 1; active low; level sensitive
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| IRQ 27 (EXT IRQ 2) JP2C CHIP ; active low; level sensitive
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| IRQ 28 (EXT IRQ 3) PCI bridge; active low; level sensitive
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| IRQ 29 (EXT IRQ 4) SystemACE IRQ; active high
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| IRQ 30 (EXT IRQ 5) SystemACE BRdy (unused)
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| IRQ 31 (EXT IRQ 6) (unused)
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+-------------------------------------------------------------------------*/
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mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
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mtdcr (UIC0ER, 0x00000000); /* disable all ints */
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mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */
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mtdcr (UIC0PR, 0xFFFFFF87); /* set int polarities */
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mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
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mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
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/* Configure the interface to the SystemACE MCU port.
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The SystemACE is fast, but there is no reason to have
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excessivly tight timings. So the settings are slightly
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generous. */
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/* EBC0_B1AP: BME=1, TWT=2, CSN=0, OEN=1,
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WBN=0, WBF=1, TH=0, RE=0, SOR=0, BEM=0, PEN=0 */
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mtdcr (EBC0_CFGADDR, PB1AP);
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mtdcr (EBC0_CFGDATA, 0x01011000);
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/* EBC0_B1CR: BAS=x, BS=0(1MB), BU=3(R/W), BW=0(8bits) */
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mtdcr (EBC0_CFGADDR, PB1CR);
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mtdcr (EBC0_CFGDATA, CONFIG_SYS_SYSTEMACE_BASE | 0x00018000);
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/* Enable the /PerWE output as /PerWE, instead of /PCIINT. */
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/* CPC0_CR1 |= PCIPW */
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mtdcr (0xb2, mfdcr (0xb2) | 0x00004000);
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return 0;
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}
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#ifdef CONFIG_BOARD_PRE_INIT
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int board_pre_init (void)
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{
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return board_early_init_f ();
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}
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#endif
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/*
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* This function is also called by arch/powerpc/lib/board.c:board_init_f (it is
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* also in the init_sequence array) but later. Many more things are
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* configured, but we are still running from flash.
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*/
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int checkboard (void)
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{
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unsigned vers, status;
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/* check that the SystemACE chip is alive. */
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printf ("ACE: ");
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vers = readw (CONFIG_SYS_SYSTEMACE_BASE + 0x16);
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printf ("SystemACE %u.%u (build %u)",
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(vers >> 12) & 0x0f, (vers >> 8) & 0x0f, vers & 0xff);
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status = readl (CONFIG_SYS_SYSTEMACE_BASE + 0x04);
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#ifdef DEBUG
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printf (" STATUS=0x%08x", status);
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#endif
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/* If the flash card is present and there is an initial error,
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then force a restart of the program. */
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if (status & 0x00000010) {
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printf (" CFDETECT");
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if (status & 0x04) {
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/* CONTROLREG = CFGPROG */
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writew (0x1000, CONFIG_SYS_SYSTEMACE_BASE + 0x18);
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udelay (500);
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/* CONTROLREG = CFGRESET */
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writew (0x0080, CONFIG_SYS_SYSTEMACE_BASE + 0x18);
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udelay (500);
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writew (0x0000, CONFIG_SYS_SYSTEMACE_BASE + 0x18);
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/* CONTROLREG = CFGSTART */
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writew (0x0020, CONFIG_SYS_SYSTEMACE_BASE + 0x18);
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status = readl (CONFIG_SYS_SYSTEMACE_BASE + 0x04);
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}
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}
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/* Wait for the SystemACE to program its chain of devices. */
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while ((status & 0x84) == 0x00) {
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udelay (500);
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status = readl (CONFIG_SYS_SYSTEMACE_BASE + 0x04);
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}
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if (status & 0x04)
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printf (" CFG-ERROR");
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if (status & 0x80)
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printf (" CFGDONE");
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printf ("\n");
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/* Force /RTS to active. The board it not wired quite
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correctly to use cts/rtc flow control, so just force the
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/RST active and forget about it. */
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writeb (readb (0xef600404) | 0x03, 0xef600404);
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printf ("JSE: ready\n");
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return 0;
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}
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/* **** No more functions called by board_init_f. **** */
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/*
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* This function is called by arch/powerpc/lib/board.c:board_init_r. At this
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* point, basic setup is done, U-Boot has been moved into SDRAM and
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* PCI has been set up. From here we done late setup.
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*/
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int misc_init_r (void)
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{
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host_bridge_init ();
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return 0;
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}
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