170 lines
3.8 KiB
C
170 lines
3.8 KiB
C
/*
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* board/mx1ads/mx1ads.c
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*
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* (c) Copyright 2004
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* Techware Information Technology, Inc.
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* http://www.techware.com.tw/
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*
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* Ming-Len Wu <minglen_wu@techware.com.tw>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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/*#include <mc9328.h>*/
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#include <asm/arch/imx-regs.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define FCLK_SPEED 1
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#if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */
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#define M_MDIV 0xC3
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#define M_PDIV 0x4
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#define M_SDIV 0x1
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#elif FCLK_SPEED==1 /* Fout = 202.8MHz */
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#define M_MDIV 0xA1
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#define M_PDIV 0x3
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#define M_SDIV 0x1
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#endif
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#define USB_CLOCK 1
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#if USB_CLOCK==0
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#define U_M_MDIV 0xA1
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#define U_M_PDIV 0x3
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#define U_M_SDIV 0x1
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#elif USB_CLOCK==1
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#define U_M_MDIV 0x48
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#define U_M_PDIV 0x3
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#define U_M_SDIV 0x2
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#endif
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#if 0
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static inline void delay (unsigned long loops)
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{
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__asm__ volatile ("1:\n"
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"subs %0, %1, #1\n"
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"bne 1b":"=r" (loops):"0" (loops));
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}
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#endif
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/*
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* Miscellaneous platform dependent initialisations
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*/
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void SetAsynchMode (void)
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{
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__asm__ ("mrc p15,0,r0,c1,c0,0 \n"
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"mov r2, #0xC0000000 \n"
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"orr r0,r2,r0 \n" "mcr p15,0,r0,c1,c0,0 \n");
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}
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static u32 mc9328sid;
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int board_init (void)
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{
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volatile unsigned int tmp;
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mc9328sid = SIDR;
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GPCR = 0x000003AB; /* I/O pad driving strength */
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/* MX1_CS1U = 0x00000A00; */ /* SRAM initialization */
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/* MX1_CS1L = 0x11110601; */
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MPCTL0 = 0x04632410; /* setting for 150 MHz MCU PLL CLK */
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/* set FCLK divider 1 (i.e. FCLK to MCU PLL CLK) and
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* BCLK divider to 2 (i.e. BCLK to 48 MHz)
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*/
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CSCR = 0xAF000403;
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CSCR |= 0x00200000; /* Trigger the restart bit(bit 21) */
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CSCR &= 0xFFFF7FFF; /* Program PRESC bit(bit 15) to 0 to divide-by-1 */
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/* setup cs4 for cs8900 ethernet */
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CS4U = 0x00000F00; /* Initialize CS4 for CS8900 ethernet */
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CS4L = 0x00001501;
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GIUS (0) &= 0xFF3FFFFF;
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GPR (0) &= 0xFF3FFFFF;
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tmp = *(unsigned int *) (0x1500000C);
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tmp = *(unsigned int *) (0x1500000C);
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SetAsynchMode ();
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gd->bd->bi_arch_number = MACH_TYPE_MX1ADS;
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gd->bd->bi_boot_params = 0x08000100; /* adress of boot parameters */
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icache_enable ();
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dcache_enable ();
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/* set PERCLKs */
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PCDR = 0x00000055; /* set PERCLKS */
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/* PERCLK3 is only used by SSI so the SSI driver can set it any value it likes
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* PERCLK1 and PERCLK2 are shared so DO NOT change it in any other place
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* all sources selected as normal interrupt
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*/
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/* MX1_INTTYPEH = 0;
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MX1_INTTYPEL = 0;
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*/
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return 0;
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}
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int board_late_init (void)
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{
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setenv ("stdout", "serial");
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setenv ("stderr", "serial");
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switch (mc9328sid) {
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case 0x0005901d:
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printf ("MX1ADS board with MC9328 MX1 (0L44N), Silicon ID 0x%08x \n\n",
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mc9328sid);
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break;
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case 0x04d4c01d:
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printf ("MX1ADS board with MC9328 MXL (1L45N), Silicon ID 0x%08x \n\n",
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mc9328sid);
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break;
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case 0x00d4c01d:
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printf ("MX1ADS board with MC9328 MXL (2L45N), Silicon ID 0x%08x \n\n",
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mc9328sid);
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break;
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default:
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printf ("MX1ADS board with UNKNOWN MC9328 cpu, Silicon ID 0x%08x \n",
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mc9328sid);
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break;
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}
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return 0;
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}
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int dram_init (void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
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return 0;
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}
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