1400a7f3d3
Add definitions for access and status. Need to drop the mixed case. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
343 lines
8.9 KiB
C
343 lines
8.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (c) 2018 Bootlin
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* Author: Miquel Raynal <miquel.raynal@bootlin.com>
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*/
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#ifndef __TPM_V2_H
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#define __TPM_V2_H
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#include <tpm-common.h>
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#define TPM2_DIGEST_LEN 32
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/**
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* TPM2 Structure Tags for command/response buffers.
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*
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* @TPM2_ST_NO_SESSIONS: the command does not need an authentication.
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* @TPM2_ST_SESSIONS: the command needs an authentication.
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*/
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enum tpm2_structures {
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TPM2_ST_NO_SESSIONS = 0x8001,
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TPM2_ST_SESSIONS = 0x8002,
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};
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/**
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* TPM2 type of boolean.
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*/
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enum tpm2_yes_no {
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TPMI_YES = 1,
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TPMI_NO = 0,
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};
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/**
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* TPM2 startup values.
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*
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* @TPM2_SU_CLEAR: reset the internal state.
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* @TPM2_SU_STATE: restore saved state (if any).
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*/
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enum tpm2_startup_types {
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TPM2_SU_CLEAR = 0x0000,
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TPM2_SU_STATE = 0x0001,
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};
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/**
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* TPM2 permanent handles.
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*
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* @TPM2_RH_OWNER: refers to the 'owner' hierarchy.
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* @TPM2_RS_PW: indicates a password.
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* @TPM2_RH_LOCKOUT: refers to the 'lockout' hierarchy.
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* @TPM2_RH_ENDORSEMENT: refers to the 'endorsement' hierarchy.
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* @TPM2_RH_PLATFORM: refers to the 'platform' hierarchy.
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*/
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enum tpm2_handles {
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TPM2_RH_OWNER = 0x40000001,
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TPM2_RS_PW = 0x40000009,
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TPM2_RH_LOCKOUT = 0x4000000A,
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TPM2_RH_ENDORSEMENT = 0x4000000B,
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TPM2_RH_PLATFORM = 0x4000000C,
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};
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/**
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* TPM2 command codes used at the beginning of a buffer, gives the command.
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*
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* @TPM2_CC_STARTUP: TPM2_Startup().
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* @TPM2_CC_SELF_TEST: TPM2_SelfTest().
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* @TPM2_CC_CLEAR: TPM2_Clear().
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* @TPM2_CC_CLEARCONTROL: TPM2_ClearControl().
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* @TPM2_CC_HIERCHANGEAUTH: TPM2_HierarchyChangeAuth().
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* @TPM2_CC_PCR_SETAUTHPOL: TPM2_PCR_SetAuthPolicy().
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* @TPM2_CC_DAM_RESET: TPM2_DictionaryAttackLockReset().
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* @TPM2_CC_DAM_PARAMETERS: TPM2_DictionaryAttackParameters().
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* @TPM2_CC_GET_CAPABILITY: TPM2_GetCapibility().
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* @TPM2_CC_PCR_READ: TPM2_PCR_Read().
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* @TPM2_CC_PCR_EXTEND: TPM2_PCR_Extend().
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* @TPM2_CC_PCR_SETAUTHVAL: TPM2_PCR_SetAuthValue().
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*/
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enum tpm2_command_codes {
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TPM2_CC_STARTUP = 0x0144,
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TPM2_CC_SELF_TEST = 0x0143,
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TPM2_CC_CLEAR = 0x0126,
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TPM2_CC_CLEARCONTROL = 0x0127,
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TPM2_CC_HIERCHANGEAUTH = 0x0129,
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TPM2_CC_PCR_SETAUTHPOL = 0x012C,
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TPM2_CC_DAM_RESET = 0x0139,
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TPM2_CC_DAM_PARAMETERS = 0x013A,
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TPM2_CC_NV_READ = 0x014E,
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TPM2_CC_GET_CAPABILITY = 0x017A,
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TPM2_CC_PCR_READ = 0x017E,
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TPM2_CC_PCR_EXTEND = 0x0182,
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TPM2_CC_PCR_SETAUTHVAL = 0x0183,
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};
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/**
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* TPM2 return codes.
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*/
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enum tpm2_return_codes {
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TPM2_RC_SUCCESS = 0x0000,
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TPM2_RC_BAD_TAG = 0x001E,
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TPM2_RC_FMT1 = 0x0080,
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TPM2_RC_HASH = TPM2_RC_FMT1 + 0x0003,
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TPM2_RC_VALUE = TPM2_RC_FMT1 + 0x0004,
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TPM2_RC_SIZE = TPM2_RC_FMT1 + 0x0015,
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TPM2_RC_BAD_AUTH = TPM2_RC_FMT1 + 0x0022,
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TPM2_RC_HANDLE = TPM2_RC_FMT1 + 0x000B,
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TPM2_RC_VER1 = 0x0100,
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TPM2_RC_INITIALIZE = TPM2_RC_VER1 + 0x0000,
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TPM2_RC_FAILURE = TPM2_RC_VER1 + 0x0001,
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TPM2_RC_DISABLED = TPM2_RC_VER1 + 0x0020,
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TPM2_RC_AUTH_MISSING = TPM2_RC_VER1 + 0x0025,
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TPM2_RC_COMMAND_CODE = TPM2_RC_VER1 + 0x0043,
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TPM2_RC_AUTHSIZE = TPM2_RC_VER1 + 0x0044,
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TPM2_RC_AUTH_CONTEXT = TPM2_RC_VER1 + 0x0045,
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TPM2_RC_NEEDS_TEST = TPM2_RC_VER1 + 0x0053,
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TPM2_RC_WARN = 0x0900,
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TPM2_RC_TESTING = TPM2_RC_WARN + 0x000A,
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TPM2_RC_REFERENCE_H0 = TPM2_RC_WARN + 0x0010,
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TPM2_RC_LOCKOUT = TPM2_RC_WARN + 0x0021,
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};
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/**
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* TPM2 algorithms.
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*/
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enum tpm2_algorithms {
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TPM2_ALG_XOR = 0x0A,
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TPM2_ALG_SHA256 = 0x0B,
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TPM2_ALG_SHA384 = 0x0C,
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TPM2_ALG_SHA512 = 0x0D,
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TPM2_ALG_NULL = 0x10,
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};
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/* NV index attributes */
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enum tpm_index_attrs {
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TPMA_NV_PPWRITE = 1UL << 0,
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TPMA_NV_OWNERWRITE = 1UL << 1,
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TPMA_NV_AUTHWRITE = 1UL << 2,
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TPMA_NV_POLICYWRITE = 1UL << 3,
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TPMA_NV_COUNTER = 1UL << 4,
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TPMA_NV_BITS = 1UL << 5,
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TPMA_NV_EXTEND = 1UL << 6,
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TPMA_NV_POLICY_DELETE = 1UL << 10,
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TPMA_NV_WRITELOCKED = 1UL << 11,
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TPMA_NV_WRITEALL = 1UL << 12,
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TPMA_NV_WRITEDEFINE = 1UL << 13,
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TPMA_NV_WRITE_STCLEAR = 1UL << 14,
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TPMA_NV_GLOBALLOCK = 1UL << 15,
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TPMA_NV_PPREAD = 1UL << 16,
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TPMA_NV_OWNERREAD = 1UL << 17,
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TPMA_NV_AUTHREAD = 1UL << 18,
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TPMA_NV_POLICYREAD = 1UL << 19,
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TPMA_NV_NO_DA = 1UL << 25,
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TPMA_NV_ORDERLY = 1UL << 26,
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TPMA_NV_CLEAR_STCLEAR = 1UL << 27,
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TPMA_NV_READLOCKED = 1UL << 28,
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TPMA_NV_WRITTEN = 1UL << 29,
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TPMA_NV_PLATFORMCREATE = 1UL << 30,
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TPMA_NV_READ_STCLEAR = 1UL << 31,
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TPMA_NV_MASK_READ = TPMA_NV_PPREAD | TPMA_NV_OWNERREAD |
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TPMA_NV_AUTHREAD | TPMA_NV_POLICYREAD,
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TPMA_NV_MASK_WRITE = TPMA_NV_PPWRITE | TPMA_NV_OWNERWRITE |
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TPMA_NV_AUTHWRITE | TPMA_NV_POLICYWRITE,
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};
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enum {
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TPM_ACCESS_VALID = 1 << 7,
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TPM_ACCESS_ACTIVE_LOCALITY = 1 << 5,
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TPM_ACCESS_REQUEST_PENDING = 1 << 2,
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TPM_ACCESS_REQUEST_USE = 1 << 1,
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TPM_ACCESS_ESTABLISHMENT = 1 << 0,
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};
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enum {
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TPM_STS_FAMILY_SHIFT = 26,
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TPM_STS_FAMILY_MASK = 0x3 << TPM_STS_FAMILY_SHIFT,
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TPM_STS_FAMILY_TPM2 = 1 << TPM_STS_FAMILY_SHIFT,
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TPM_STS_RESE_TESTABLISMENT_BIT = 1 << 25,
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TPM_STS_COMMAND_CANCEL = 1 << 24,
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TPM_STS_BURST_COUNT_SHIFT = 8,
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TPM_STS_BURST_COUNT_MASK = 0xffff << TPM_STS_BURST_COUNT_SHIFT,
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TPM_STS_VALID = 1 << 7,
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TPM_STS_COMMAND_READY = 1 << 6,
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TPM_STS_GO = 1 << 5,
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TPM_STS_DATA_AVAIL = 1 << 4,
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TPM_STS_DATA_EXPECT = 1 << 3,
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TPM_STS_SELF_TEST_DONE = 1 << 2,
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TPM_STS_RESPONSE_RETRY = 1 << 1,
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};
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enum {
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TPM_CMD_COUNT_OFFSET = 2,
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TPM_CMD_ORDINAL_OFFSET = 6,
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TPM_MAX_BUF_SIZE = 1260,
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};
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/**
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* Issue a TPM2_Startup command.
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*
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* @dev TPM device
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* @mode TPM startup mode
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*
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* @return code of the operation
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*/
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u32 tpm2_startup(struct udevice *dev, enum tpm2_startup_types mode);
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/**
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* Issue a TPM2_SelfTest command.
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*
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* @dev TPM device
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* @full_test Asking to perform all tests or only the untested ones
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*
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* @return code of the operation
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*/
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u32 tpm2_self_test(struct udevice *dev, enum tpm2_yes_no full_test);
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/**
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* Issue a TPM2_Clear command.
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*
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* @dev TPM device
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* @handle Handle
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* @pw Password
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* @pw_sz Length of the password
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*
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* @return code of the operation
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*/
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u32 tpm2_clear(struct udevice *dev, u32 handle, const char *pw,
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const ssize_t pw_sz);
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/**
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* Issue a TPM2_PCR_Extend command.
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*
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* @dev TPM device
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* @index Index of the PCR
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* @digest Value representing the event to be recorded
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*
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* @return code of the operation
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*/
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u32 tpm2_pcr_extend(struct udevice *dev, u32 index, const uint8_t *digest);
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/**
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* Issue a TPM2_PCR_Read command.
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*
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* @dev TPM device
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* @idx Index of the PCR
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* @idx_min_sz Minimum size in bytes of the pcrSelect array
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* @data Output buffer for contents of the named PCR
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* @updates Optional out parameter: number of updates for this PCR
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*
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* @return code of the operation
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*/
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u32 tpm2_pcr_read(struct udevice *dev, u32 idx, unsigned int idx_min_sz,
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void *data, unsigned int *updates);
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/**
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* Issue a TPM2_GetCapability command. This implementation is limited
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* to query property index that is 4-byte wide.
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*
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* @dev TPM device
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* @capability Partition of capabilities
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* @property Further definition of capability, limited to be 4 bytes wide
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* @buf Output buffer for capability information
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* @prop_count Size of output buffer
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*
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* @return code of the operation
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*/
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u32 tpm2_get_capability(struct udevice *dev, u32 capability, u32 property,
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void *buf, size_t prop_count);
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/**
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* Issue a TPM2_DictionaryAttackLockReset command.
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*
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* @dev TPM device
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* @pw Password
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* @pw_sz Length of the password
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*
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* @return code of the operation
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*/
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u32 tpm2_dam_reset(struct udevice *dev, const char *pw, const ssize_t pw_sz);
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/**
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* Issue a TPM2_DictionaryAttackParameters command.
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*
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* @dev TPM device
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* @pw Password
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* @pw_sz Length of the password
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* @max_tries Count of authorizations before lockout
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* @recovery_time Time before decrementation of the failure count
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* @lockout_recovery Time to wait after a lockout
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*
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* @return code of the operation
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*/
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u32 tpm2_dam_parameters(struct udevice *dev, const char *pw,
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const ssize_t pw_sz, unsigned int max_tries,
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unsigned int recovery_time,
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unsigned int lockout_recovery);
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/**
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* Issue a TPM2_HierarchyChangeAuth command.
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*
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* @dev TPM device
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* @handle Handle
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* @newpw New password
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* @newpw_sz Length of the new password
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* @oldpw Old password
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* @oldpw_sz Length of the old password
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*
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* @return code of the operation
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*/
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int tpm2_change_auth(struct udevice *dev, u32 handle, const char *newpw,
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const ssize_t newpw_sz, const char *oldpw,
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const ssize_t oldpw_sz);
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/**
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* Issue a TPM_PCR_SetAuthPolicy command.
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*
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* @dev TPM device
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* @pw Platform password
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* @pw_sz Length of the password
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* @index Index of the PCR
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* @digest New key to access the PCR
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*
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* @return code of the operation
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*/
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u32 tpm2_pcr_setauthpolicy(struct udevice *dev, const char *pw,
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const ssize_t pw_sz, u32 index, const char *key);
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/**
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* Issue a TPM_PCR_SetAuthValue command.
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*
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* @dev TPM device
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* @pw Platform password
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* @pw_sz Length of the password
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* @index Index of the PCR
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* @digest New key to access the PCR
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* @key_sz Length of the new key
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*
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* @return code of the operation
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*/
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u32 tpm2_pcr_setauthvalue(struct udevice *dev, const char *pw,
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const ssize_t pw_sz, u32 index, const char *key,
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const ssize_t key_sz);
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#endif /* __TPM_V2_H */
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