60b295672d
For e500mc cores the watchdog timer period has to be set by means of a 6bit value, that defines the bit of the timebase counter used to signal a watchdog timer exception on its 0 to 1 transition. The macro used to set the watchdog period TCR_WP, was redefined for e500mc to support 6 WP setting. The parameter (x) given to the macro specifies the prescaling factor of the time base clock (fTB): watchdog_period = 1/fTB * 2^x Signed-off-by: Rainer Boschung <rainer.boschung@keymile.com> Reviewed-by: York Sun <yorksun@freescale.com> |
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arc | ||
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avr32 | ||
blackfin | ||
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microblaze | ||
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nds32 | ||
nios2 | ||
openrisc | ||
powerpc | ||
sandbox | ||
sh | ||
sparc | ||
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.gitignore |