20a58ac0d8
Even though existing implementation works fine in preparation to submission of ARCv2 architecture we need this change. In case of ARCv2 interrupt vector table consists of just addresses of corresponding handlers. And if those addresses will be in .text section then assembler will encode them as everything in .text section as middle-endian and then on real execution CPU will read swapped addresses and will jump into the wild. Once introduced new section is situated so .text section remains the first which allows us to use common linker option for linking everything to a specified CONFIG_SYS_TEXT_BASE. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Igor Guryanov <guryanov@synopsys.com>
22 lines
550 B
Makefile
22 lines
550 B
Makefile
#
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# SPDX-License-Identifier: GPL-2.0+
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#
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libs-y += arch/arc/cpu/$(CPU)/
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libs-y += arch/arc/lib/
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# MetaWare debugger doesn't support PIE (position-independent executable)
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# so the only way to load U-Boot in MDB is to fake it by:
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# 1. Reset PIE flag in ELF header
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# 2. Strip all debug information from elf
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ifdef CONFIG_SYS_LITTLE_ENDIAN
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EXEC_TYPE_OFFSET=16
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else
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EXEC_TYPE_OFFSET=17
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endif
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mdbtrick: u-boot
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$(Q)printf '\x02' | dd of=u-boot bs=1 seek=$(EXEC_TYPE_OFFSET) count=1 \
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conv=notrunc &> /dev/null
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$(Q)$(CROSS_COMPILE)strip -g u-boot
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