c4b8bc48b6
This is mostly unused. In the case where it is currently used, it means the same as CONFIG_SPL_PAD_TO, which is already set for the platform. Signed-off-by: Tom Rini <trini@konsulko.com>
49 lines
1.3 KiB
C
49 lines
1.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2012 Atmel Corporation
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* Copyright (C) 2019 Stefan Roese <sr@denx.de>
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*
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* Configuation settings for the GARDENA smart Gateway (AT91SAM9G25)
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*/
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#ifndef __CONFIG_H__
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#define __CONFIG_H__
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#ifndef __ASSEMBLY__
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#include <linux/bitops.h>
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#endif
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/* ARM asynchronous clock */
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#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
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#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
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/* SDRAM */
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#define CONFIG_SYS_SDRAM_BASE 0x20000000
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#define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */
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/* NAND flash */
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_BASE 0x40000000
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#define CONFIG_SYS_NAND_DBW_8 1
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/* our ALE is AD21 */
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#define CONFIG_SYS_NAND_MASK_ALE BIT(21)
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/* our CLE is AD22 */
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#define CONFIG_SYS_NAND_MASK_CLE BIT(22)
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#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4
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#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5
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/* SPL */
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#define CONFIG_SYS_MONITOR_LEN (512 << 10)
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#define CONFIG_SYS_MASTER_CLOCK 132096000
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#define CONFIG_SYS_AT91_PLLA 0x20c73f03
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#define CONFIG_SYS_MCKR 0x1301
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#define CONFIG_SYS_MCKR_CSS 0x1302
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#define CONFIG_SYS_NAND_U_BOOT_SIZE 0xa0000
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
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#endif
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