c2ae7d8220
Move the SPL settings into common/spl where most of the SPL code is kept. Signed-off-by: Simon Glass <sjg@chromium.org>
18 lines
491 B
Plaintext
18 lines
491 B
Plaintext
CONFIG_ARM=y
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CONFIG_ARCH_SUNXI=y
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CONFIG_MACH_SUN6I=y
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CONFIG_DRAM_ZQ=251
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CONFIG_MMC_SUNXI_SLOT_EXTRA=2
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CONFIG_USB1_VBUS_PIN="PH24"
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CONFIG_USB2_VBUS_PIN=""
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CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-mixtile-loftq"
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# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
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CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPA(21)"
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CONFIG_SPL=y
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# CONFIG_CMD_IMLS is not set
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# CONFIG_CMD_FLASH is not set
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# CONFIG_CMD_FPGA is not set
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CONFIG_ETH_DESIGNWARE=y
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CONFIG_AXP_ALDO1_VOLT=3300
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CONFIG_USB_EHCI_HCD=y
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