u-boot/arch/riscv/cpu
Bin Meng 85c714d8dc riscv: Adjust board_get_usable_ram_top() for 32-bit
When testing QEMU RISC-V 'virt' machine with a 2 GiB memory
configuration, it was discovered gd->ram_top is assigned to
value zero in setup_dest_addr().

While gd->ram_top should not be declared as type `unsigned long`,
which will be updated in a future patch, the current logic in
board_get_usable_ram_top() can be updated to cover both 64-bit
and 32-bit RISC-V.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
2021-02-03 03:38:41 -07:00
..
ax25 timer: Add _TIMER suffix to Andes PLMT Kconfig 2020-10-26 10:01:28 +08:00
fu540 riscv: Adjust board_get_usable_ram_top() for 32-bit 2021-02-03 03:38:41 -07:00
generic riscv: Adjust board_get_usable_ram_top() for 32-bit 2021-02-03 03:38:41 -07:00
cpu.c riscv: Clear pending IPIs on initialization 2020-09-30 08:54:52 +08:00
Makefile riscv: Move trap handler codes to mtrap.S 2018-12-18 09:56:27 +08:00
mtrap.S riscv: Add option to print registers on exception 2020-02-10 14:51:08 +08:00
start.S riscv: fix the wrong swap value register 2020-12-14 15:16:34 +08:00
u-boot-spl.lds riscv: Add _image_binary_end for SPL 2020-06-04 09:44:08 +08:00
u-boot.lds riscv: Fix breakage caused by linker relaxation 2020-02-10 14:50:53 +08:00