f76d88b060
Enable DP_PWR signal to power the DP to HDMI converter cable. Signed-off-by: Wen He <wen.he_1@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
225 lines
7.1 KiB
C
225 lines
7.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2019 NXP
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*/
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#ifndef __L1028A_COMMON_H
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#define __L1028A_COMMON_H
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#define CONFIG_REMAKE_ELF
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#define CONFIG_FSL_LAYERSCAPE
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#define CONFIG_MP
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#include <asm/arch/stream_id_lsch3.h>
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#include <asm/arch/config.h>
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#include <asm/arch/soc.h>
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/* Link Definitions */
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#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
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#define CONFIG_SKIP_LOWLEVEL_INIT
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#define CONFIG_VERY_BIG_RAM
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#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
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#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
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#define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
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#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 1
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#define CONFIG_CMD_MEMTEST
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#define CONFIG_SYS_MEMTEST_START 0x80000000
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#define CONFIG_SYS_MEMTEST_END 0x9fffffff
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/*
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* SMP Definitinos
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*/
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#define CPU_RELEASE_ADDR secondary_boot_func
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/* Generic Timer Definitions */
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#define COUNTER_FREQUENCY 25000000 /* 25MHz */
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/* Size of malloc() pool */
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
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/* I2C */
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#ifndef CONFIG_DM_I2C
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#define CONFIG_SYS_I2C
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#endif
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/* Serial Port */
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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/* Miscellaneous configurable options */
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#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
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/* Physical Memory Map */
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#define CONFIG_CHIP_SELECTS_PER_CTRL 4
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#define CONFIG_HWCONFIG
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#define HWCONFIG_BUFFER_SIZE 128
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/* Allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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#define BOOT_TARGET_DEVICES(func) \
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func(MMC, mmc, 0) \
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func(MMC, mmc, 1) \
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func(USB, usb, 0)
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#include <config_distro_bootcmd.h>
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/* Initial environment variables */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"board=ls1028ardb\0" \
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"hwconfig=fsl_ddr:bank_intlv=auto\0" \
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"ramdisk_addr=0x800000\0" \
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"ramdisk_size=0x2000000\0" \
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"fdt_high=0xffffffffffffffff\0" \
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"initrd_high=0xffffffffffffffff\0" \
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"fdt_addr=0x00f00000\0" \
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"kernel_addr=0x01000000\0" \
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"scriptaddr=0x80000000\0" \
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"scripthdraddr=0x80080000\0" \
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"fdtheader_addr_r=0x80100000\0" \
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"kernelheader_addr_r=0x80200000\0" \
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"load_addr=0xa0000000\0" \
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"kernel_addr_r=0x81000000\0" \
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"fdt_addr_r=0x90000000\0" \
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"ramdisk_addr_r=0xa0000000\0" \
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"kernel_start=0x1000000\0" \
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"kernelheader_start=0x800000\0" \
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"kernel_load=0xa0000000\0" \
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"kernel_size=0x2800000\0" \
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"kernelheader_size=0x40000\0" \
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"kernel_addr_sd=0x8000\0" \
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"kernel_size_sd=0x14000\0" \
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"kernelhdr_addr_sd=0x4000\0" \
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"kernelhdr_size_sd=0x10\0" \
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"console=ttyS0,115200\0" \
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"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
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BOOTENV \
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"boot_scripts=ls1028ardb_boot.scr\0" \
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"boot_script_hdr=hdr_ls1028ardb_bs.out\0" \
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"scan_dev_for_boot_part=" \
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"part list ${devtype} ${devnum} devplist; " \
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"env exists devplist || setenv devplist 1; " \
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"for distro_bootpart in ${devplist}; do " \
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"if fstype ${devtype} " \
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"${devnum}:${distro_bootpart} " \
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"bootfstype; then " \
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"run scan_dev_for_boot; " \
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"fi; " \
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"done\0" \
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"scan_dev_for_boot=" \
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"echo Scanning ${devtype} " \
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"${devnum}:${distro_bootpart}...; " \
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"for prefix in ${boot_prefixes}; do " \
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"run scan_dev_for_scripts; " \
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"done;" \
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"\0" \
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"boot_a_script=" \
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"load ${devtype} ${devnum}:${distro_bootpart} " \
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"${scriptaddr} ${prefix}${script}; " \
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"env exists secureboot && load ${devtype} " \
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"${devnum}:${distro_bootpart} " \
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"${scripthdraddr} ${prefix}${boot_script_hdr} " \
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"&& esbc_validate ${scripthdraddr};" \
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"source ${scriptaddr}\0" \
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"xspi_bootcmd=echo Trying load from FlexSPI flash ...;" \
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"sf probe 0:0 && sf read $load_addr " \
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"$kernel_start $kernel_size ; env exists secureboot &&" \
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"sf read $kernelheader_addr_r $kernelheader_start " \
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"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
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" bootm $load_addr#$board\0" \
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"xspi_hdploadcmd=echo Trying load HDP firmware from FlexSPI...;" \
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"sf probe 0:0 && sf read $load_addr 0x940000 0x30000 " \
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"&& hdp load $load_addr 0x2000\0" \
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"sd_bootcmd=echo Trying load from SD ...;" \
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"mmcinfo; mmc read $load_addr " \
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"$kernel_addr_sd $kernel_size_sd && " \
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"env exists secureboot && mmc read $kernelheader_addr_r " \
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"$kernelhdr_addr_sd $kernelhdr_size_sd " \
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" && esbc_validate ${kernelheader_addr_r};" \
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"bootm $load_addr#$board\0" \
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"sd_hdploadcmd=echo Trying load HDP firmware from SD..;" \
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"mmcinfo;mmc read $load_addr 0x4a00 0x200 " \
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"&& hdp load $load_addr 0x2000\0" \
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"emmc_bootcmd=echo Trying load from EMMC ..;" \
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"mmcinfo; mmc dev 1; mmc read $load_addr " \
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"$kernel_addr_sd $kernel_size_sd && " \
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"env exists secureboot && mmc read $kernelheader_addr_r " \
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"$kernelhdr_addr_sd $kernelhdr_size_sd " \
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" && esbc_validate ${kernelheader_addr_r};" \
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"bootm $load_addr#$board\0" \
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"emmc_hdploadcmd=echo Trying load HDP firmware from EMMC..;" \
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"mmc dev 1;mmcinfo;mmc read $load_addr 0x4a00 0x200 " \
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"&& hdp load $load_addr 0x2000\0"
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#undef CONFIG_BOOTCOMMAND
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#define XSPI_NOR_BOOTCOMMAND \
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"run xspi_hdploadcmd; run distro_bootcmd; run xspi_bootcmd; " \
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"env exists secureboot && esbc_halt;;"
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#define SD_BOOTCOMMAND \
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"run sd_hdploadcmd; run distro_bootcmd;run sd_bootcmd; " \
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"env exists secureboot && esbc_halt;"
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#define SD2_BOOTCOMMAND \
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"run emmc_hdploadcmd; run distro_bootcmd;run emmc_bootcmd; " \
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"env exists secureboot && esbc_halt;"
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/* Monitor Command Prompt */
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#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
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sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
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#ifndef CONFIG_CMDLINE_EDITING
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#define CONFIG_CMDLINE_EDITING 1
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#endif
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#define CONFIG_SYS_MAXARGS 64 /* max command args */
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#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
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/* MMC */
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#ifdef CONFIG_MMC
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#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
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#endif
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#define CONFIG_SYS_MMC_ENV_DEV 0
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#define OCRAM_NONSECURE_SIZE 0x00010000
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#define CONFIG_SYS_FSL_QSPI_BASE 0x20000000
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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/* I2C bus multiplexer */
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#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
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#define I2C_MUX_CH_DEFAULT 0x8
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/* EEPROM */
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#define CONFIG_ID_EEPROM
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#define CONFIG_SYS_I2C_EEPROM_NXID
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#define CONFIG_SYS_EEPROM_BUS_NUM 0
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
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/* DisplayPort */
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#define DP_PWD_EN_DEFAULT_MASK 0x8
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#ifdef CONFIG_NXP_ESBC
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#include <asm/fsl_secure_boot.h>
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#endif
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/* Ethernet */
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/* smallest ENETC BD ring has 8 entries */
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#define CONFIG_SYS_RX_ETH_BUFFER 8
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#endif /* __L1028A_COMMON_H */
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