9db1bfa110
This is a port of the official PLL errata workaround from Freescale to mainline u-boot. The PLL's in the i.MX51 processor can go out of lock due to a metastable condition in an analog flip-flop when used at high frequencies. This workaround implements an undocumented feature in the PLL (dither mode), which causes the effect of this failure to be much lower (in terms of frequency deviation), avoiding system failure, or at least decreasing the likelihood of system failure. Signed-off-by: David Jander <david@protonic.nl>
18 lines
786 B
Plaintext
18 lines
786 B
Plaintext
U-Boot for Freescale i.MX5x
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This file contains information for the port of U-Boot to the Freescale
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i.MX5x SoCs.
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1. CONFIGURATION OPTIONS/SETTINGS
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---------------------------------
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1.1 CONFIG_MX51_PLL_ERRATA: Workaround for i.MX51 PLL errata.
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This option should be enabled by all boards using the i.MX51 silicon
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version up until (including) 3.0 running at 800MHz.
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The PLL's in the i.MX51 processor can go out of lock due to a metastable
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condition in an analog flip-flop when used at high frequencies.
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This workaround implements an undocumented feature in the PLL (dither
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mode), which causes the effect of this failure to be much lower (in terms
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of frequency deviation), avoiding system failure, or at least decreasing
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the likelihood of system failure.
|