f6220f1a86
mrccache implementation can be common for all boards. Move it from ivybridge cpu directory to the common lib directory. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
32 lines
731 B
Plaintext
32 lines
731 B
Plaintext
CONFIG_X86=y
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CONFIG_VENDOR_GOOGLE=y
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CONFIG_DEFAULT_DEVICE_TREE="chromebox_panther"
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CONFIG_TARGET_CHROMEBOX_PANTHER=y
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CONFIG_HAVE_MRC=y
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CONFIG_ENABLE_MRC_CACHE=y
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CONFIG_HAVE_VGA_BIOS=y
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# CONFIG_CMD_IMLS is not set
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# CONFIG_CMD_FLASH is not set
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# CONFIG_CMD_SETEXPR is not set
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# CONFIG_CMD_NFS is not set
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CONFIG_BOOTSTAGE=y
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CONFIG_BOOTSTAGE_REPORT=y
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CONFIG_CMD_BOOTSTAGE=y
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CONFIG_CMD_TPM=y
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CONFIG_CMD_TPM_TEST=y
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CONFIG_OF_CONTROL=y
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CONFIG_CMD_CROS_EC=y
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CONFIG_CROS_EC=y
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CONFIG_CROS_EC_LPC=y
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CONFIG_SPI_FLASH=y
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CONFIG_DM_PCI=y
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CONFIG_DM_RTC=y
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CONFIG_DM_TPM=y
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CONFIG_TPM_TIS_LPC=y
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CONFIG_VIDEO_VESA=y
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CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
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CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
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CONFIG_USE_PRIVATE_LIBGCC=y
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CONFIG_SYS_VSNPRINTF=y
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CONFIG_TPM=y
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