470 lines
10 KiB
ArmAsm
470 lines
10 KiB
ArmAsm
/*
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* armboot - Startup Code for S3C6400/ARM1176 CPU-core
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*
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* Copyright (c) 2007 Samsung Electronics
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*
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* Copyright (C) 2008
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* Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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* 2007-09-21 - Restructured codes by jsgood (jsgood.yang@samsung.com)
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* 2007-09-21 - Added MoviNAND and OneNAND boot codes by
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* jsgood (jsgood.yang@samsung.com)
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* Base codes by scsuh (sc.suh)
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*/
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#include <config.h>
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#include <version.h>
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#ifdef CONFIG_ENABLE_MMU
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#include <asm/proc/domain.h>
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#endif
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#include <s3c6400.h>
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#if !defined(CONFIG_ENABLE_MMU) && !defined(CONFIG_SYS_PHY_UBOOT_BASE)
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#define CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_UBOOT_BASE
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#endif
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/*
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*************************************************************************
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*
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* Jump vector table as in table 3.1 in [1]
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*
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*************************************************************************
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*/
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.globl _start
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_start: b reset
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#ifndef CONFIG_NAND_SPL
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ldr pc, _undefined_instruction
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ldr pc, _software_interrupt
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ldr pc, _prefetch_abort
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ldr pc, _data_abort
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ldr pc, _not_used
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ldr pc, _irq
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ldr pc, _fiq
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_undefined_instruction:
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.word undefined_instruction
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_software_interrupt:
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.word software_interrupt
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_prefetch_abort:
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.word prefetch_abort
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_data_abort:
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.word data_abort
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_not_used:
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.word not_used
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_irq:
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.word irq
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_fiq:
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.word fiq
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_pad:
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.word 0x12345678 /* now 16*4=64 */
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#else
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. = _start + 64
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#endif
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.global _end_vect
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_end_vect:
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.balignl 16,0xdeadbeef
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/*
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*************************************************************************
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*
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* Startup Code (reset vector)
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*
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* do important init only if we don't start from memory!
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* setup Memory and board specific bits prior to relocation.
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* relocate armboot to ram
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* setup stack
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*
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*************************************************************************
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*/
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_TEXT_BASE:
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.word TEXT_BASE
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/*
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* Below variable is very important because we use MMU in U-Boot.
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* Without it, we cannot run code correctly before MMU is ON.
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* by scsuh.
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*/
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_TEXT_PHY_BASE:
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.word CONFIG_SYS_PHY_UBOOT_BASE
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.globl _armboot_start
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_armboot_start:
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.word _start
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/*
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* These are defined in the board-specific linker script.
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*/
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.globl _bss_start
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_bss_start:
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.word __bss_start
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.globl _bss_end
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_bss_end:
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.word _end
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/*
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* the actual reset code
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*/
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reset:
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/*
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* set the cpu to SVC32 mode
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*/
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mrs r0, cpsr
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bic r0, r0, #0x3f
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orr r0, r0, #0xd3
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msr cpsr, r0
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/*
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*************************************************************************
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*
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* CPU_init_critical registers
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*
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* setup important registers
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* setup memory timing
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*
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*************************************************************************
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*/
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/*
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* we do sys-critical inits only at reboot,
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* not when booting from ram!
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*/
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cpu_init_crit:
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/*
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* When booting from NAND - it has definitely been a reset, so, no need
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* to flush caches and disable the MMU
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*/
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#ifndef CONFIG_NAND_SPL
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/*
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* flush v4 I/D caches
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*/
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mov r0, #0
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mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
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mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
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/*
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* disable MMU stuff and caches
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*/
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mrc p15, 0, r0, c1, c0, 0
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bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
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bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
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orr r0, r0, #0x00000002 @ set bit 2 (A) Align
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orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
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/* Prepare to disable the MMU */
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adr r1, mmu_disable_phys
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/* We presume we're within the first 1024 bytes */
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and r1, r1, #0x3fc
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ldr r2, _TEXT_PHY_BASE
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ldr r3, =0xfff00000
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and r2, r2, r3
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orr r2, r2, r1
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b mmu_disable
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.align 5
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/* Run in a single cache-line */
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mmu_disable:
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mcr p15, 0, r0, c1, c0, 0
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nop
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nop
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mov pc, r2
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#endif
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mmu_disable_phys:
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/* Peri port setup */
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ldr r0, =0x70000000
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orr r0, r0, #0x13
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mcr p15,0,r0,c15,c2,4 @ 256M (0x70000000 - 0x7fffffff)
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/*
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* Go setup Memory and board specific bits prior to relocation.
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*/
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bl lowlevel_init /* go setup pll,mux,memory */
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after_copy:
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#ifdef CONFIG_ENABLE_MMU
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enable_mmu:
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/* enable domain access */
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ldr r5, =0x0000ffff
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mcr p15, 0, r5, c3, c0, 0 /* load domain access register */
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/* Set the TTB register */
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ldr r0, _mmu_table_base
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ldr r1, =CONFIG_SYS_PHY_UBOOT_BASE
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ldr r2, =0xfff00000
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bic r0, r0, r2
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orr r1, r0, r1
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mcr p15, 0, r1, c2, c0, 0
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/* Enable the MMU */
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mrc p15, 0, r0, c1, c0, 0
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orr r0, r0, #1 /* Set CR_M to enable MMU */
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/* Prepare to enable the MMU */
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adr r1, skip_hw_init
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and r1, r1, #0x3fc
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ldr r2, _TEXT_BASE
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ldr r3, =0xfff00000
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and r2, r2, r3
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orr r2, r2, r1
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b mmu_enable
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.align 5
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/* Run in a single cache-line */
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mmu_enable:
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mcr p15, 0, r0, c1, c0, 0
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nop
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nop
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mov pc, r2
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#endif
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skip_hw_init:
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/* Set up the stack */
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stack_setup:
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#ifdef CONFIG_MEMORY_UPPER_CODE
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ldr sp, =(CONFIG_SYS_UBOOT_BASE + CONFIG_SYS_UBOOT_SIZE - 0xc)
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#else
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ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
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sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
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sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
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sub sp, r0, #12 /* leave 3 words for abort-stack */
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#endif
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clear_bss:
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ldr r0, _bss_start /* find start of bss segment */
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ldr r1, _bss_end /* stop here */
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mov r2, #0 /* clear */
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clbss_l:
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str r2, [r0] /* clear loop... */
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add r0, r0, #4
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cmp r0, r1
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ble clbss_l
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#ifndef CONFIG_NAND_SPL
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ldr pc, _start_armboot
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_start_armboot:
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.word start_armboot
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#else
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b nand_boot
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/* .word nand_boot*/
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#endif
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#ifdef CONFIG_ENABLE_MMU
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_mmu_table_base:
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.word mmu_table
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#endif
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#ifndef CONFIG_NAND_SPL
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/*
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* we assume that cache operation is done before. (eg. cleanup_before_linux())
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* actually, we don't need to do anything about cache if not use d-cache in
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* U-Boot. So, in this function we clean only MMU. by scsuh
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*
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* void theLastJump(void *kernel, int arch_num, uint boot_params);
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*/
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#ifdef CONFIG_ENABLE_MMU
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.globl theLastJump
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theLastJump:
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mov r9, r0
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ldr r3, =0xfff00000
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ldr r4, _TEXT_PHY_BASE
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adr r5, phy_last_jump
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bic r5, r5, r3
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orr r5, r5, r4
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mov pc, r5
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phy_last_jump:
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/*
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* disable MMU stuff
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*/
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mrc p15, 0, r0, c1, c0, 0
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bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */
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bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
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orr r0, r0, #0x00000002 /* set bit 2 (A) Align */
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orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
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mcr p15, 0, r0, c1, c0, 0
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mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
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mov r0, #0
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mov pc, r9
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#endif
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/*
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*************************************************************************
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*
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* Interrupt handling
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*
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*************************************************************************
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*/
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@
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@ IRQ stack frame.
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@
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#define S_FRAME_SIZE 72
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#define S_OLD_R0 68
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#define S_PSR 64
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#define S_PC 60
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#define S_LR 56
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#define S_SP 52
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#define S_IP 48
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#define S_FP 44
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#define S_R10 40
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#define S_R9 36
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#define S_R8 32
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#define S_R7 28
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#define S_R6 24
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#define S_R5 20
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#define S_R4 16
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#define S_R3 12
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#define S_R2 8
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#define S_R1 4
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#define S_R0 0
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#define MODE_SVC 0x13
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#define I_BIT 0x80
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/*
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* use bad_save_user_regs for abort/prefetch/undef/swi ...
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*/
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.macro bad_save_user_regs
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/* carve out a frame on current user stack */
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sub sp, sp, #S_FRAME_SIZE
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/* Save user registers (now in svc mode) r0-r12 */
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stmia sp, {r0 - r12}
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ldr r2, _armboot_start
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sub r2, r2, #(CONFIG_SYS_MALLOC_LEN)
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/* set base 2 words into abort stack */
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sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8)
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/* get values for "aborted" pc and cpsr (into parm regs) */
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ldmia r2, {r2 - r3}
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/* grab pointer to old stack */
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add r0, sp, #S_FRAME_SIZE
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add r5, sp, #S_SP
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mov r1, lr
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/* save sp_SVC, lr_SVC, pc, cpsr */
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stmia r5, {r0 - r3}
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/* save current stack into r0 (param register) */
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mov r0, sp
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.endm
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.macro get_bad_stack
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/* setup our mode stack (enter in banked mode) */
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ldr r13, _armboot_start
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/* move past malloc pool */
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sub r13, r13, #(CONFIG_SYS_MALLOC_LEN)
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/* move to reserved a couple spots for abort stack */
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sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE + 8)
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/* save caller lr in position 0 of saved stack */
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str lr, [r13]
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/* get the spsr */
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mrs lr, spsr
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/* save spsr in position 1 of saved stack */
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str lr, [r13, #4]
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/* prepare SVC-Mode */
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mov r13, #MODE_SVC
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@ msr spsr_c, r13
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/* switch modes, make sure moves will execute */
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msr spsr, r13
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/* capture return pc */
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mov lr, pc
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/* jump to next instruction & switch modes. */
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movs pc, lr
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.endm
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.macro get_bad_stack_swi
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/* space on current stack for scratch reg. */
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sub r13, r13, #4
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/* save R0's value. */
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str r0, [r13]
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/* get data regions start */
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ldr r0, _armboot_start
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/* move past malloc pool */
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sub r0, r0, #(CONFIG_SYS_MALLOC_LEN)
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/* move past gbl and a couple spots for abort stack */
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sub r0, r0, #(CONFIG_SYS_GBL_DATA_SIZE + 8)
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/* save caller lr in position 0 of saved stack */
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str lr, [r0]
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/* get the spsr */
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mrs r0, spsr
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/* save spsr in position 1 of saved stack */
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str lr, [r0, #4]
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/* restore r0 */
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ldr r0, [r13]
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/* pop stack entry */
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add r13, r13, #4
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.endm
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/*
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* exception handlers
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*/
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.align 5
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undefined_instruction:
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get_bad_stack
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bad_save_user_regs
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bl do_undefined_instruction
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.align 5
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software_interrupt:
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get_bad_stack_swi
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bad_save_user_regs
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bl do_software_interrupt
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.align 5
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prefetch_abort:
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get_bad_stack
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bad_save_user_regs
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bl do_prefetch_abort
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.align 5
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data_abort:
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get_bad_stack
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bad_save_user_regs
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bl do_data_abort
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.align 5
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not_used:
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get_bad_stack
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bad_save_user_regs
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bl do_not_used
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.align 5
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irq:
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get_bad_stack
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bad_save_user_regs
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bl do_irq
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.align 5
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fiq:
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get_bad_stack
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bad_save_user_regs
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bl do_fiq
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#endif /* CONFIG_NAND_SPL */
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