aba3924927
>From revision J the board uses new phy chip LAN8710. Compared with RTL8201, RA17 pin is TXERR. It has pullup which causes phy not to work. To fix this PA17 is muxed with GMAC function. This makes the pin output-low. Signed-off-by: Stefan Mavrodiev <stefan@olimex.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
87 lines
2.7 KiB
C
87 lines
2.7 KiB
C
#include <common.h>
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#include <netdev.h>
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#include <miiphy.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/gpio.h>
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void eth_init_board(void)
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{
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int pin;
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struct sunxi_ccm_reg *const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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/* Set up clock gating */
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#ifdef CONFIG_SUNXI_GEN_SUN6I
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setbits_le32(&ccm->ahb_reset0_cfg, 0x1 << AHB_RESET_OFFSET_GMAC);
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setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_GMAC);
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#else
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setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC);
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#endif
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/* Set MII clock */
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#ifdef CONFIG_RGMII
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setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
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CCM_GMAC_CTRL_GPIT_RGMII);
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setbits_le32(&ccm->gmac_clk_cfg,
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CCM_GMAC_CTRL_TX_CLK_DELAY(CONFIG_GMAC_TX_DELAY));
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#else
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setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_MII |
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CCM_GMAC_CTRL_GPIT_MII);
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#endif
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#ifndef CONFIG_MACH_SUN6I
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/* Configure pin mux settings for GMAC */
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#ifdef CONFIG_SUN7I_GMAC_FORCE_TXERR
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for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(17); pin++) {
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#else
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for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) {
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#endif
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#ifdef CONFIG_RGMII
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/* skip unused pins in RGMII mode */
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if (pin == SUNXI_GPA(9) || pin == SUNXI_GPA(14))
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continue;
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#endif
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sunxi_gpio_set_cfgpin(pin, SUN7I_GPA_GMAC);
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sunxi_gpio_set_drv(pin, 3);
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}
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#elif defined CONFIG_RGMII
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/* Configure sun6i RGMII mode pin mux settings */
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for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++) {
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sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
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sunxi_gpio_set_drv(pin, 3);
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}
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for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
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sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
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sunxi_gpio_set_drv(pin, 3);
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}
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for (pin = SUNXI_GPA(19); pin <= SUNXI_GPA(20); pin++) {
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sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
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sunxi_gpio_set_drv(pin, 3);
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}
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for (pin = SUNXI_GPA(25); pin <= SUNXI_GPA(27); pin++) {
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sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
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sunxi_gpio_set_drv(pin, 3);
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}
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#elif defined CONFIG_GMII
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/* Configure sun6i GMII mode pin mux settings */
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for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(27); pin++) {
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sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
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sunxi_gpio_set_drv(pin, 2);
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}
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#else
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/* Configure sun6i MII mode pin mux settings */
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for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++)
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sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
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for (pin = SUNXI_GPA(8); pin <= SUNXI_GPA(9); pin++)
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sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
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for (pin = SUNXI_GPA(11); pin <= SUNXI_GPA(14); pin++)
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sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
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for (pin = SUNXI_GPA(19); pin <= SUNXI_GPA(24); pin++)
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sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
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for (pin = SUNXI_GPA(26); pin <= SUNXI_GPA(27); pin++)
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sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
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#endif
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}
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