u-boot/board/freescale/b4860qds
York Sun 316f0d0f8f powerpc: mpc85xx: Fix static TLB table for SDRAM
Most predefined TLB tables don't have memory coherence bit set for
SDRAM. This wasn't an issue before invalidate_dcache_range() function
was enabled. Without the coherence bit, dcache invalidation doesn't
automatically flush the cache. The coherence bit is already set when
dynamic TLB table is used. For some boards with different SPL boot
method, or with legacy fixed setting, this bit needs to be set in
TLB files.

Signed-off-by: York Sun <york.sun@nxp.com>
2017-12-06 14:54:12 -08:00
..
b4_pbi.cfg board/b4860qds:Slow MDC clock to comply IEEE specs in PBI config 2014-04-22 17:58:47 -07:00
b4_rcw.cfg powerpc/b4860/pbl: fix rcw cfg 2014-01-02 14:10:14 -08:00
b4860qds_crossbar_con.h powerpc: B4420: Remove macro CONFIG_PPC_B4420 2016-11-23 23:42:12 -08:00
b4860qds_qixis.h SGMII:fix PHY addresses for QSGMII Riser Card working in SGMII mode 2013-10-16 16:13:11 -07:00
b4860qds.c env: Rename some other getenv()-related functions 2017-08-16 08:31:11 -04:00
b4860qds.h Add GPL-2.0+ SPDX-License-Identifier to source files 2013-07-24 09:44:38 -04:00
ddr.c board_f: Rename initdram() to dram_init() 2017-04-13 09:40:57 -04:00
eth_b4860qds.c powerpc: B4420: Remove macro CONFIG_PPC_B4420 2016-11-23 23:42:12 -08:00
Kconfig NXP: Introduce board/freescale/common/Kconfig and migrate CHAIN_OF_TRUST 2017-01-24 10:33:59 -05:00
law.c powerpc/b4860: Enable law creation of MAPLE 2014-12-05 08:06:12 -08:00
MAINTAINERS powerpc: fsl: Update maintainers 2017-06-12 12:18:37 -07:00
Makefile powerpc: B4860QDS: Remove macro CONFIG_B4860QDS 2016-11-23 23:42:12 -08:00
pci.c Add GPL-2.0+ SPDX-License-Identifier to source files 2013-07-24 09:44:38 -04:00
spl.c env: Add an enum for environment state 2017-08-15 08:18:51 -04:00
tlb.c powerpc: mpc85xx: Fix static TLB table for SDRAM 2017-12-06 14:54:12 -08:00