e35b6497f4
It is possible to boot U-Boot for chromebook_coral either 'bare metal' or from coreboot. In the latter case we want to provide access to the coreboot sysinfo tables. Move the definitions into a file available to any x86 board. Signed-off-by: Simon Glass <sjg@chromium.org>
47 lines
1.1 KiB
C
47 lines
1.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* UART support for U-Boot when launched from Coreboot
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*
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* Copyright 2019 Google LLC
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*/
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#include <common.h>
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#include <dm.h>
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#include <ns16550.h>
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#include <serial.h>
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#include <asm/cb_sysinfo.h>
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static int coreboot_of_to_plat(struct udevice *dev)
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{
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struct ns16550_plat *plat = dev_get_plat(dev);
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struct cb_serial *cb_info = lib_sysinfo.serial;
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plat->base = cb_info->baseaddr;
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plat->reg_shift = cb_info->regwidth == 4 ? 2 : 0;
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plat->reg_width = cb_info->regwidth;
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plat->clock = cb_info->input_hertz;
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plat->fcr = UART_FCR_DEFVAL;
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plat->flags = 0;
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if (cb_info->type == CB_SERIAL_TYPE_IO_MAPPED)
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plat->flags |= NS16550_FLAG_IO;
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return 0;
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}
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static const struct udevice_id coreboot_serial_ids[] = {
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{ .compatible = "coreboot-serial" },
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{ },
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};
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U_BOOT_DRIVER(coreboot_uart) = {
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.name = "coreboot_uart",
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.id = UCLASS_SERIAL,
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.of_match = coreboot_serial_ids,
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.priv_auto = sizeof(struct ns16550),
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.plat_auto = sizeof(struct ns16550_plat),
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.of_to_plat = coreboot_of_to_plat,
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.probe = ns16550_serial_probe,
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.ops = &ns16550_serial_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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