699c4e592b
Initially IVT for ARCv2 was simply copypasted from ARCompact with some selected fixes so basic stuff works. Now we update it with more ARCv2 specific vectors like * Software Interrupt * Division by zero * Data cache consistency error * Misaligned access Also normal interrupts are now implemented properly and extened to all possible 240 items. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
170 lines
3.6 KiB
C
170 lines
3.6 KiB
C
/*
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* Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arcregs.h>
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#include <asm/ptrace.h>
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/* Bit values in STATUS32 */
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#define E1_MASK (1 << 1) /* Level 1 interrupts enable */
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#define E2_MASK (1 << 2) /* Level 2 interrupts enable */
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int interrupt_init(void)
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{
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return 0;
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}
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/*
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* returns true if interrupts had been enabled before we disabled them
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*/
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int disable_interrupts(void)
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{
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int status = read_aux_reg(ARC_AUX_STATUS32);
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int state = (status & (E1_MASK | E2_MASK)) ? 1 : 0;
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status &= ~(E1_MASK | E2_MASK);
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/* STATUS32 register is updated indirectly with "FLAG" instruction */
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__asm__("flag %0" : : "r" (status));
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return state;
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}
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void enable_interrupts(void)
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{
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unsigned int status = read_aux_reg(ARC_AUX_STATUS32);
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status |= E1_MASK | E2_MASK;
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/* STATUS32 register is updated indirectly with "FLAG" instruction */
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__asm__("flag %0" : : "r" (status));
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}
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static void print_reg_file(long *reg_rev, int start_num)
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{
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unsigned int i;
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/* Print 3 registers per line */
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for (i = start_num; i < start_num + 25; i++) {
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printf("r%02u: 0x%08lx\t", i, (unsigned long)*reg_rev);
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if (((i + 1) % 3) == 0)
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printf("\n");
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/* Because pt_regs has registers reversed */
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reg_rev--;
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}
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/* Add new-line if none was inserted in the end of loop above */
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if (((i + 1) % 3) != 0)
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printf("\n");
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}
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void show_regs(struct pt_regs *regs)
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{
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printf("ECR:\t0x%08lx\n", regs->ecr);
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printf("RET:\t0x%08lx\nBLINK:\t0x%08lx\nSTAT32:\t0x%08lx\n",
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regs->ret, regs->blink, regs->status32);
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printf("GP: 0x%08lx\t r25: 0x%08lx\t\n", regs->r26, regs->r25);
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printf("BTA: 0x%08lx\t SP: 0x%08lx\t FP: 0x%08lx\n", regs->bta,
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regs->sp, regs->fp);
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printf("LPS: 0x%08lx\tLPE: 0x%08lx\tLPC: 0x%08lx\n", regs->lp_start,
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regs->lp_end, regs->lp_count);
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print_reg_file(&(regs->r0), 0);
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}
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void bad_mode(struct pt_regs *regs)
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{
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if (regs)
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show_regs(regs);
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panic("Resetting CPU ...\n");
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}
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void do_memory_error(unsigned long address, struct pt_regs *regs)
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{
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printf("Memory error exception @ 0x%lx\n", address);
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bad_mode(regs);
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}
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void do_instruction_error(unsigned long address, struct pt_regs *regs)
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{
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printf("Instruction error exception @ 0x%lx\n", address);
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bad_mode(regs);
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}
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void do_machine_check_fault(unsigned long address, struct pt_regs *regs)
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{
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printf("Machine check exception @ 0x%lx\n", address);
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bad_mode(regs);
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}
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void do_interrupt_handler(void)
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{
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printf("Interrupt fired\n");
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bad_mode(0);
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}
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void do_itlb_miss(struct pt_regs *regs)
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{
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printf("I TLB miss exception\n");
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bad_mode(regs);
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}
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void do_dtlb_miss(struct pt_regs *regs)
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{
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printf("D TLB miss exception\n");
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bad_mode(regs);
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}
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void do_tlb_prot_violation(unsigned long address, struct pt_regs *regs)
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{
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printf("TLB protection violation or misaligned access @ 0x%lx\n",
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address);
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bad_mode(regs);
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}
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void do_privilege_violation(struct pt_regs *regs)
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{
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printf("Privilege violation exception\n");
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bad_mode(regs);
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}
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void do_trap(struct pt_regs *regs)
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{
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printf("Trap exception\n");
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bad_mode(regs);
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}
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void do_extension(struct pt_regs *regs)
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{
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printf("Extension instruction exception\n");
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bad_mode(regs);
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}
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#ifdef CONFIG_ISA_ARCV2
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void do_swi(struct pt_regs *regs)
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{
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printf("Software Interrupt exception\n");
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bad_mode(regs);
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}
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void do_divzero(unsigned long address, struct pt_regs *regs)
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{
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printf("Division by zero exception @ 0x%lx\n", address);
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bad_mode(regs);
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}
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void do_dcerror(struct pt_regs *regs)
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{
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printf("Data cache consistency error exception\n");
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bad_mode(regs);
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}
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void do_maligned(unsigned long address, struct pt_regs *regs)
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{
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printf("Misaligned data access exception @ 0x%lx\n", address);
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bad_mode(regs);
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}
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#endif
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