527 lines
13 KiB
C
527 lines
13 KiB
C
/*
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* (C) Copyright 2002 Wolfgang Grandegger, wg@denx.de.
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*
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* This driver for AMD PCnet network controllers is derived from the
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* Linux driver pcnet32.c written 1996-1999 by Thomas Bogendoerfer.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <malloc.h>
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#include <net.h>
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#include <asm/io.h>
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#include <pci.h>
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#if 0
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#define PCNET_DEBUG_LEVEL 0 /* 0=off, 1=init, 2=rx/tx */
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#endif
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#if PCNET_DEBUG_LEVEL > 0
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#define PCNET_DEBUG1(fmt,args...) printf (fmt ,##args)
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#if PCNET_DEBUG_LEVEL > 1
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#define PCNET_DEBUG2(fmt,args...) printf (fmt ,##args)
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#else
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#define PCNET_DEBUG2(fmt,args...)
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#endif
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#else
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#define PCNET_DEBUG1(fmt,args...)
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#define PCNET_DEBUG2(fmt,args...)
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#endif
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#if defined(CONFIG_CMD_NET) \
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&& defined(CONFIG_NET_MULTI) && defined(CONFIG_PCNET)
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#if !defined(CONF_PCNET_79C973) && defined(CONF_PCNET_79C975)
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#error "Macro for PCnet chip version is not defined!"
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#endif
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/*
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* Set the number of Tx and Rx buffers, using Log_2(# buffers).
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* Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
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* That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
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*/
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#define PCNET_LOG_TX_BUFFERS 0
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#define PCNET_LOG_RX_BUFFERS 2
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#define TX_RING_SIZE (1 << (PCNET_LOG_TX_BUFFERS))
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#define TX_RING_LEN_BITS ((PCNET_LOG_TX_BUFFERS) << 12)
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#define RX_RING_SIZE (1 << (PCNET_LOG_RX_BUFFERS))
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#define RX_RING_LEN_BITS ((PCNET_LOG_RX_BUFFERS) << 4)
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#define PKT_BUF_SZ 1544
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/* The PCNET Rx and Tx ring descriptors. */
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struct pcnet_rx_head {
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u32 base;
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s16 buf_length;
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s16 status;
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u32 msg_length;
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u32 reserved;
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};
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struct pcnet_tx_head {
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u32 base;
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s16 length;
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s16 status;
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u32 misc;
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u32 reserved;
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};
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/* The PCNET 32-Bit initialization block, described in databook. */
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struct pcnet_init_block {
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u16 mode;
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u16 tlen_rlen;
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u8 phys_addr[6];
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u16 reserved;
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u32 filter[2];
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/* Receive and transmit ring base, along with extra bits. */
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u32 rx_ring;
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u32 tx_ring;
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u32 reserved2;
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};
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typedef struct pcnet_priv {
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struct pcnet_rx_head rx_ring[RX_RING_SIZE];
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struct pcnet_tx_head tx_ring[TX_RING_SIZE];
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struct pcnet_init_block init_block;
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/* Receive Buffer space */
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unsigned char rx_buf[RX_RING_SIZE][PKT_BUF_SZ + 4];
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int cur_rx;
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int cur_tx;
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} pcnet_priv_t;
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static pcnet_priv_t *lp;
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/* Offsets from base I/O address for WIO mode */
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#define PCNET_RDP 0x10
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#define PCNET_RAP 0x12
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#define PCNET_RESET 0x14
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#define PCNET_BDP 0x16
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static u16 pcnet_read_csr (struct eth_device *dev, int index)
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{
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outw (index, dev->iobase+PCNET_RAP);
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return inw (dev->iobase+PCNET_RDP);
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}
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static void pcnet_write_csr (struct eth_device *dev, int index, u16 val)
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{
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outw (index, dev->iobase+PCNET_RAP);
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outw (val, dev->iobase+PCNET_RDP);
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}
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static u16 pcnet_read_bcr (struct eth_device *dev, int index)
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{
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outw (index, dev->iobase+PCNET_RAP);
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return inw (dev->iobase+PCNET_BDP);
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}
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static void pcnet_write_bcr (struct eth_device *dev, int index, u16 val)
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{
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outw (index, dev->iobase+PCNET_RAP);
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outw (val, dev->iobase+PCNET_BDP);
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}
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static void pcnet_reset (struct eth_device *dev)
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{
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inw (dev->iobase+PCNET_RESET);
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}
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static int pcnet_check (struct eth_device *dev)
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{
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outw (88, dev->iobase+PCNET_RAP);
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return (inw (dev->iobase+PCNET_RAP) == 88);
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}
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static int pcnet_init( struct eth_device* dev, bd_t *bis);
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static int pcnet_send (struct eth_device* dev, volatile void *packet,
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int length);
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static int pcnet_recv (struct eth_device* dev);
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static void pcnet_halt (struct eth_device* dev);
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static int pcnet_probe(struct eth_device* dev, bd_t *bis, int dev_num);
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#define PCI_TO_MEM(d,a) pci_phys_to_mem((pci_dev_t)d->priv, (u_long)(a))
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#define PCI_TO_MEM_LE(d,a) (u32)(cpu_to_le32(PCI_TO_MEM(d,a)))
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static struct pci_device_id supported[] = {
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{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE },
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{ }
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};
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int pcnet_initialize(bd_t *bis)
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{
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pci_dev_t devbusfn;
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struct eth_device* dev;
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u16 command, status;
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int dev_nr = 0;
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PCNET_DEBUG1("\npcnet_initialize...\n");
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for (dev_nr = 0; ; dev_nr++) {
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/*
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* Find the PCnet PCI device(s).
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*/
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if ((devbusfn = pci_find_devices(supported, dev_nr)) < 0) {
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break;
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}
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/*
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* Allocate and pre-fill the device structure.
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*/
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dev = (struct eth_device*) malloc(sizeof *dev);
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dev->priv = (void *)devbusfn;
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sprintf(dev->name, "pcnet#%d", dev_nr);
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/*
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* Setup the PCI device.
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*/
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pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, (unsigned int *)&dev->iobase);
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dev->iobase &= ~0xf;
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PCNET_DEBUG1("%s: devbusfn=0x%x iobase=0x%x: ",
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dev->name, devbusfn, dev->iobase);
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command = PCI_COMMAND_IO | PCI_COMMAND_MASTER;
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pci_write_config_word(devbusfn, PCI_COMMAND, command);
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pci_read_config_word(devbusfn, PCI_COMMAND, &status);
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if ((status & command) != command) {
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printf("%s: Couldn't enable IO access or Bus Mastering\n",
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dev->name);
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free(dev);
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continue;
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}
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pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x40);
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/*
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* Probe the PCnet chip.
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*/
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if (pcnet_probe(dev, bis, dev_nr) < 0) {
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free(dev);
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continue;
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}
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/*
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* Setup device structure and register the driver.
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*/
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dev->init = pcnet_init;
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dev->halt = pcnet_halt;
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dev->send = pcnet_send;
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dev->recv = pcnet_recv;
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eth_register(dev);
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}
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udelay(10 * 1000);
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return dev_nr;
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}
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static int pcnet_probe(struct eth_device* dev, bd_t *bis, int dev_nr)
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{
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int chip_version;
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char *chipname;
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#ifdef PCNET_HAS_PROM
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int i;
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#endif
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/* Reset the PCnet controller */
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pcnet_reset(dev);
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/* Check if register access is working */
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if (pcnet_read_csr(dev, 0) != 4 || !pcnet_check(dev)) {
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printf("%s: CSR register access check failed\n", dev->name);
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return -1;
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}
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/* Identify the chip */
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chip_version = pcnet_read_csr(dev, 88) | (pcnet_read_csr(dev,89) << 16);
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if ((chip_version & 0xfff) != 0x003)
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return -1;
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chip_version = (chip_version >> 12) & 0xffff;
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switch (chip_version) {
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#ifdef CONFIG_PCNET_79C973
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case 0x2625:
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chipname = "PCnet/FAST III 79C973"; /* PCI */
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break;
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#endif
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#ifdef CONFIG_PCNET_79C975
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case 0x2627:
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chipname = "PCnet/FAST III 79C975"; /* PCI */
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break;
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#endif
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default:
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printf("%s: PCnet version %#x not supported\n",
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dev->name, chip_version);
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return -1;
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}
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PCNET_DEBUG1("AMD %s\n", chipname);
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#ifdef PCNET_HAS_PROM
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/*
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* In most chips, after a chip reset, the ethernet address is read from
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* the station address PROM at the base address and programmed into the
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* "Physical Address Registers" CSR12-14.
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*/
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for (i = 0; i < 3; i++) {
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unsigned int val;
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val = pcnet_read_csr(dev, i+12) & 0x0ffff;
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/* There may be endianness issues here. */
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dev->enetaddr[2*i ] = val & 0x0ff;
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dev->enetaddr[2*i+1] = (val >> 8) & 0x0ff;
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}
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#endif /* PCNET_HAS_PROM */
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return 0;
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}
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static int pcnet_init(struct eth_device* dev, bd_t *bis)
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{
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int i, val;
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u32 addr;
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PCNET_DEBUG1("%s: pcnet_init...\n", dev->name);
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/* Switch pcnet to 32bit mode */
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pcnet_write_bcr (dev, 20, 2);
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#ifdef CONFIG_PN62
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/* Setup LED registers */
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val = pcnet_read_bcr (dev, 2) | 0x1000;
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pcnet_write_bcr (dev, 2, val); /* enable LEDPE */
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pcnet_write_bcr (dev, 4, 0x5080); /* 100MBit */
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pcnet_write_bcr (dev, 5, 0x40c0); /* LNKSE */
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pcnet_write_bcr (dev, 6, 0x4090); /* TX Activity */
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pcnet_write_bcr (dev, 7, 0x4084); /* RX Activity */
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#endif
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/* Set/reset autoselect bit */
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val = pcnet_read_bcr (dev, 2) & ~2;
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val |= 2;
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pcnet_write_bcr (dev, 2, val);
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/* Enable auto negotiate, setup, disable fd */
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val = pcnet_read_bcr(dev, 32) & ~0x98;
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val |= 0x20;
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pcnet_write_bcr(dev, 32, val);
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/*
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* We only maintain one structure because the drivers will never
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* be used concurrently. In 32bit mode the RX and TX ring entries
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* must be aligned on 16-byte boundaries.
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*/
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if (lp == NULL) {
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addr = (u32)malloc(sizeof(pcnet_priv_t) + 0x10);
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addr = (addr + 0xf) & ~0xf;
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lp = (pcnet_priv_t *)addr;
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}
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lp->init_block.mode = cpu_to_le16(0x0000);
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lp->init_block.filter[0] = 0x00000000;
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lp->init_block.filter[1] = 0x00000000;
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/*
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* Initialize the Rx ring.
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*/
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lp->cur_rx = 0;
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for (i = 0; i < RX_RING_SIZE; i++) {
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lp->rx_ring[i].base = PCI_TO_MEM_LE(dev, lp->rx_buf[i]);
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lp->rx_ring[i].buf_length = cpu_to_le16(-PKT_BUF_SZ);
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lp->rx_ring[i].status = cpu_to_le16(0x8000);
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PCNET_DEBUG1("Rx%d: base=0x%x buf_length=0x%hx status=0x%hx\n",
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i, lp->rx_ring[i].base, lp->rx_ring[i].buf_length,
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lp->rx_ring[i].status);
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}
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/*
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* Initialize the Tx ring. The Tx buffer address is filled in as
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* needed, but we do need to clear the upper ownership bit.
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*/
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lp->cur_tx = 0;
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for (i = 0; i < TX_RING_SIZE; i++) {
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lp->tx_ring[i].base = 0;
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lp->tx_ring[i].status = 0;
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}
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/*
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* Setup Init Block.
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*/
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PCNET_DEBUG1("Init block at 0x%p: MAC", &lp->init_block);
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for (i = 0; i < 6; i++) {
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lp->init_block.phys_addr[i] = dev->enetaddr[i];
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PCNET_DEBUG1(" %02x", lp->init_block.phys_addr[i]);
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}
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lp->init_block.tlen_rlen = cpu_to_le16(TX_RING_LEN_BITS |
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RX_RING_LEN_BITS);
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lp->init_block.rx_ring = PCI_TO_MEM_LE(dev, lp->rx_ring);
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lp->init_block.tx_ring = PCI_TO_MEM_LE(dev, lp->tx_ring);
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PCNET_DEBUG1("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n",
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lp->init_block.tlen_rlen,
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lp->init_block.rx_ring, lp->init_block.tx_ring);
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/*
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* Tell the controller where the Init Block is located.
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*/
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addr = PCI_TO_MEM(dev, &lp->init_block);
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pcnet_write_csr(dev, 1, addr & 0xffff);
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pcnet_write_csr(dev, 2, (addr >> 16) & 0xffff);
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pcnet_write_csr (dev, 4, 0x0915);
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pcnet_write_csr (dev, 0, 0x0001); /* start */
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/* Wait for Init Done bit */
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for (i = 10000; i > 0; i--) {
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if (pcnet_read_csr (dev, 0) & 0x0100)
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break;
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udelay(10);
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}
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if (i <= 0) {
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printf("%s: TIMEOUT: controller init failed\n", dev->name);
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pcnet_reset (dev);
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return 0;
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}
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/*
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* Finally start network controller operation.
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*/
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pcnet_write_csr (dev, 0, 0x0002);
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return 1;
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}
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static int pcnet_send(struct eth_device* dev, volatile void *packet, int pkt_len)
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{
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int i, status;
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struct pcnet_tx_head *entry = &lp->tx_ring[lp->cur_tx];
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PCNET_DEBUG2("Tx%d: %d bytes from 0x%p ", lp->cur_tx, pkt_len, packet);
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/* Wait for completion by testing the OWN bit */
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for (i = 1000; i > 0; i--) {
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status = le16_to_cpu(entry->status);
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if ((status & 0x8000) == 0)
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break;
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udelay(100);
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PCNET_DEBUG2(".");
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}
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if (i <= 0) {
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printf("%s: TIMEOUT: Tx%d failed (status = 0x%x)\n",
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dev->name, lp->cur_tx, status);
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pkt_len = 0;
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goto failure;
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}
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/*
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* Setup Tx ring. Caution: the write order is important here,
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* set the status with the "ownership" bits last.
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*/
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status = 0x8300;
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entry->length = le16_to_cpu(-pkt_len);
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entry->misc = 0x00000000;
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entry->base = PCI_TO_MEM_LE(dev, packet);
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entry->status = le16_to_cpu(status);
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/* Trigger an immediate send poll. */
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pcnet_write_csr (dev, 0, 0x0008);
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failure:
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if (++lp->cur_tx >= TX_RING_SIZE)
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lp->cur_tx = 0;
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PCNET_DEBUG2("done\n");
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return pkt_len;
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}
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static int pcnet_recv(struct eth_device* dev)
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{
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struct pcnet_rx_head *entry;
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int pkt_len = 0;
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u16 status;
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while (1) {
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entry = &lp->rx_ring[lp->cur_rx];
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/*
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* If we own the next entry, it's a new packet. Send it up.
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*/
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if (((status = le16_to_cpu(entry->status)) & 0x8000) != 0) {
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break;
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}
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status >>= 8;
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if (status != 0x03) { /* There was an error. */
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printf("%s: Rx%d", dev->name, lp->cur_rx);
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PCNET_DEBUG1(" (status=0x%x)", status);
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if (status & 0x20) printf(" Frame");
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if (status & 0x10) printf(" Overflow");
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if (status & 0x08) printf(" CRC");
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if (status & 0x04) printf(" Fifo");
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printf(" Error\n");
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entry->status &= le16_to_cpu(0x03ff);
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} else {
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pkt_len = (le32_to_cpu(entry->msg_length) & 0xfff) - 4;
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if (pkt_len < 60) {
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printf("%s: Rx%d: invalid packet length %d\n",
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dev->name, lp->cur_rx, pkt_len);
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} else {
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NetReceive(lp->rx_buf[lp->cur_rx], pkt_len);
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PCNET_DEBUG2("Rx%d: %d bytes from 0x%p\n",
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lp->cur_rx, pkt_len, lp->rx_buf[lp->cur_rx]);
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|
}
|
|
}
|
|
entry->status |= cpu_to_le16(0x8000);
|
|
|
|
if (++lp->cur_rx >= RX_RING_SIZE)
|
|
lp->cur_rx = 0;
|
|
}
|
|
return pkt_len;
|
|
}
|
|
|
|
static void pcnet_halt(struct eth_device* dev)
|
|
{
|
|
int i;
|
|
|
|
PCNET_DEBUG1("%s: pcnet_halt...\n", dev->name);
|
|
|
|
/* Reset the PCnet controller */
|
|
pcnet_reset (dev);
|
|
|
|
/* Wait for Stop bit */
|
|
for (i = 1000; i > 0; i--) {
|
|
if (pcnet_read_csr (dev, 0) & 0x4)
|
|
break;
|
|
udelay(10);
|
|
}
|
|
if (i <= 0) {
|
|
printf("%s: TIMEOUT: controller reset failed\n", dev->name);
|
|
}
|
|
}
|
|
|
|
#endif
|