401d1c4f5d
Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
462 lines
11 KiB
C
462 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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*
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* (C) Copyright 2000-2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*
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* Support for DM and DT, non-DM code removed.
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* Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
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*
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* TODO: fsl_dspi.c should work as a driver for the DSPI module.
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*/
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#include <common.h>
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#include <dm.h>
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#include <log.h>
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#include <asm/global_data.h>
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#include <dm/platform_data/spi_coldfire.h>
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#include <spi.h>
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#include <malloc.h>
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#include <asm/coldfire/dspi.h>
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#include <asm/io.h>
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struct coldfire_spi_priv {
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struct dspi *regs;
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uint baudrate;
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int mode;
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int charbit;
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};
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DECLARE_GLOBAL_DATA_PTR;
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#ifndef CONFIG_SPI_IDLE_VAL
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#if defined(CONFIG_SPI_MMC)
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#define CONFIG_SPI_IDLE_VAL 0xFFFF
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#else
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#define CONFIG_SPI_IDLE_VAL 0x0
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#endif
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#endif
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/*
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* DSPI specific mode
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*
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* bit 31 - 28: Transfer size 3 to 16 bits
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* 27 - 26: PCS to SCK delay prescaler
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* 25 - 24: After SCK delay prescaler
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* 23 - 22: Delay after transfer prescaler
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* 21 : Allow overwrite for bit 31-22 and bit 20-8
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* 20 : Double baud rate
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* 19 - 16: PCS to SCK delay scaler
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* 15 - 12: After SCK delay scaler
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* 11 - 8: Delay after transfer scaler
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* 7 - 0: SPI_CPHA, SPI_CPOL, SPI_LSB_FIRST
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*/
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#define SPI_MODE_MOD 0x00200000
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#define SPI_MODE_DBLRATE 0x00100000
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#define SPI_MODE_XFER_SZ_MASK 0xf0000000
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#define SPI_MODE_DLY_PRE_MASK 0x0fc00000
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#define SPI_MODE_DLY_SCA_MASK 0x000fff00
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#define MCF_FRM_SZ_16BIT DSPI_CTAR_TRSZ(0xf)
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#define MCF_DSPI_SPEED_BESTMATCH 0x7FFFFFFF
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#define MCF_DSPI_MAX_CTAR_REGS 8
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/* Default values */
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#define MCF_DSPI_DEFAULT_SCK_FREQ 10000000
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#define MCF_DSPI_DEFAULT_MAX_CS 4
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#define MCF_DSPI_DEFAULT_MODE 0
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#define MCF_DSPI_DEFAULT_CTAR (DSPI_CTAR_TRSZ(7) | \
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DSPI_CTAR_PCSSCK_1CLK | \
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DSPI_CTAR_PASC(0) | \
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DSPI_CTAR_PDT(0) | \
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DSPI_CTAR_CSSCK(0) | \
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DSPI_CTAR_ASC(0) | \
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DSPI_CTAR_DT(1) | \
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DSPI_CTAR_BR(6))
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#define MCF_CTAR_MODE_MASK (MCF_FRM_SZ_16BIT | \
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DSPI_CTAR_PCSSCK(3) | \
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DSPI_CTAR_PASC_7CLK | \
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DSPI_CTAR_PDT(3) | \
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DSPI_CTAR_CSSCK(0x0f) | \
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DSPI_CTAR_ASC(0x0f) | \
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DSPI_CTAR_DT(0x0f))
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#define setup_ctrl(ctrl, cs) ((ctrl & 0xFF000000) | ((1 << cs) << 16))
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static inline void cfspi_tx(struct coldfire_spi_priv *cfspi,
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u32 ctrl, u16 data)
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{
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/*
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* Need to check fifo level here
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*/
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while ((readl(&cfspi->regs->sr) & 0x0000F000) >= 0x4000)
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;
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writel(ctrl | data, &cfspi->regs->tfr);
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}
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static inline u16 cfspi_rx(struct coldfire_spi_priv *cfspi)
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{
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while ((readl(&cfspi->regs->sr) & 0x000000F0) == 0)
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;
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return readw(&cfspi->regs->rfr);
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}
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static int coldfire_spi_claim_bus(struct udevice *dev)
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{
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struct udevice *bus = dev->parent;
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struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
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struct dspi *dspi = cfspi->regs;
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struct dm_spi_slave_plat *slave_plat =
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dev_get_parent_plat(dev);
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if ((in_be32(&dspi->sr) & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
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return -1;
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/* Clear FIFO and resume transfer */
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clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
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dspi_chip_select(slave_plat->cs);
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return 0;
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}
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static int coldfire_spi_release_bus(struct udevice *dev)
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{
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struct udevice *bus = dev->parent;
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struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
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struct dspi *dspi = cfspi->regs;
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struct dm_spi_slave_plat *slave_plat =
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dev_get_parent_plat(dev);
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/* Clear FIFO */
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clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
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dspi_chip_unselect(slave_plat->cs);
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return 0;
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}
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static int coldfire_spi_xfer(struct udevice *dev, unsigned int bitlen,
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const void *dout, void *din,
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unsigned long flags)
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{
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struct udevice *bus = dev_get_parent(dev);
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struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
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struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
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u16 *spi_rd16 = NULL, *spi_wr16 = NULL;
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u8 *spi_rd = NULL, *spi_wr = NULL;
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static u32 ctrl;
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uint len = bitlen >> 3;
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if (cfspi->charbit == 16) {
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bitlen >>= 1;
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spi_wr16 = (u16 *)dout;
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spi_rd16 = (u16 *)din;
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} else {
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spi_wr = (u8 *)dout;
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spi_rd = (u8 *)din;
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}
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if ((flags & SPI_XFER_BEGIN) == SPI_XFER_BEGIN)
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ctrl |= DSPI_TFR_CONT;
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ctrl = setup_ctrl(ctrl, slave_plat->cs);
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if (len > 1) {
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int tmp_len = len - 1;
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while (tmp_len--) {
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if (dout) {
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if (cfspi->charbit == 16)
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cfspi_tx(cfspi, ctrl, *spi_wr16++);
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else
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cfspi_tx(cfspi, ctrl, *spi_wr++);
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cfspi_rx(cfspi);
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}
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if (din) {
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cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL);
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if (cfspi->charbit == 16)
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*spi_rd16++ = cfspi_rx(cfspi);
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else
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*spi_rd++ = cfspi_rx(cfspi);
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}
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}
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len = 1; /* remaining byte */
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}
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if (flags & SPI_XFER_END)
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ctrl &= ~DSPI_TFR_CONT;
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if (len) {
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if (dout) {
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if (cfspi->charbit == 16)
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cfspi_tx(cfspi, ctrl, *spi_wr16);
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else
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cfspi_tx(cfspi, ctrl, *spi_wr);
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cfspi_rx(cfspi);
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}
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if (din) {
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cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL);
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if (cfspi->charbit == 16)
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*spi_rd16 = cfspi_rx(cfspi);
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else
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*spi_rd = cfspi_rx(cfspi);
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}
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} else {
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/* dummy read */
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cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL);
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cfspi_rx(cfspi);
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}
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return 0;
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}
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static int coldfire_spi_set_speed(struct udevice *bus, uint max_hz)
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{
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struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
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struct dspi *dspi = cfspi->regs;
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int prescaler[] = { 2, 3, 5, 7 };
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int scaler[] = {
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2, 4, 6, 8,
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16, 32, 64, 128,
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256, 512, 1024, 2048,
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4096, 8192, 16384, 32768
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};
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int i, j, pbrcnt, brcnt, diff, tmp, dbr = 0;
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int best_i, best_j, bestmatch = MCF_DSPI_SPEED_BESTMATCH, baud_speed;
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u32 bus_setup;
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cfspi->baudrate = max_hz;
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/* Read current setup */
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bus_setup = readl(&dspi->ctar[dev_seq(bus)]);
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tmp = (prescaler[3] * scaler[15]);
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/* Maximum and minimum baudrate it can handle */
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if ((cfspi->baudrate > (gd->bus_clk >> 1)) ||
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(cfspi->baudrate < (gd->bus_clk / tmp))) {
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printf("Exceed baudrate limitation: Max %d - Min %d\n",
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(int)(gd->bus_clk >> 1), (int)(gd->bus_clk / tmp));
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return -1;
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}
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/* Activate Double Baud when it exceed 1/4 the bus clk */
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if ((bus_setup & DSPI_CTAR_DBR) ||
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(cfspi->baudrate > (gd->bus_clk / (prescaler[0] * scaler[0])))) {
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bus_setup |= DSPI_CTAR_DBR;
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dbr = 1;
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}
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/* Overwrite default value set in platform configuration file */
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if (cfspi->mode & SPI_MODE_MOD) {
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/*
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* Check to see if it is enabled by default in platform
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* config, or manual setting passed by mode parameter
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*/
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if (cfspi->mode & SPI_MODE_DBLRATE) {
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bus_setup |= DSPI_CTAR_DBR;
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dbr = 1;
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}
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}
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pbrcnt = sizeof(prescaler) / sizeof(int);
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brcnt = sizeof(scaler) / sizeof(int);
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/* baudrate calculation - to closer value, may not be exact match */
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for (best_i = 0, best_j = 0, i = 0; i < pbrcnt; i++) {
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baud_speed = gd->bus_clk / prescaler[i];
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for (j = 0; j < brcnt; j++) {
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tmp = (baud_speed / scaler[j]) * (1 + dbr);
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if (tmp > cfspi->baudrate)
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diff = tmp - cfspi->baudrate;
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else
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diff = cfspi->baudrate - tmp;
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if (diff < bestmatch) {
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bestmatch = diff;
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best_i = i;
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best_j = j;
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}
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}
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}
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bus_setup &= ~(DSPI_CTAR_PBR(0x03) | DSPI_CTAR_BR(0x0f));
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bus_setup |= (DSPI_CTAR_PBR(best_i) | DSPI_CTAR_BR(best_j));
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writel(bus_setup, &dspi->ctar[dev_seq(bus)]);
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return 0;
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}
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static int coldfire_spi_set_mode(struct udevice *bus, uint mode)
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{
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struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
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struct dspi *dspi = cfspi->regs;
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u32 bus_setup = 0;
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cfspi->mode = mode;
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if (cfspi->mode & SPI_CPOL)
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bus_setup |= DSPI_CTAR_CPOL;
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if (cfspi->mode & SPI_CPHA)
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bus_setup |= DSPI_CTAR_CPHA;
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if (cfspi->mode & SPI_LSB_FIRST)
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bus_setup |= DSPI_CTAR_LSBFE;
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/* Overwrite default value set in platform configuration file */
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if (cfspi->mode & SPI_MODE_MOD) {
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if ((cfspi->mode & SPI_MODE_XFER_SZ_MASK) == 0)
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bus_setup |=
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readl(&dspi->ctar[dev_seq(bus)]) & MCF_FRM_SZ_16BIT;
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else
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bus_setup |=
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((cfspi->mode & SPI_MODE_XFER_SZ_MASK) >> 1);
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/* PSCSCK, PASC, PDT */
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bus_setup |= (cfspi->mode & SPI_MODE_DLY_PRE_MASK) >> 4;
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/* CSSCK, ASC, DT */
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bus_setup |= (cfspi->mode & SPI_MODE_DLY_SCA_MASK) >> 4;
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} else {
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bus_setup |=
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(readl(&dspi->ctar[dev_seq(bus)]) & MCF_CTAR_MODE_MASK);
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}
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cfspi->charbit =
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((readl(&dspi->ctar[dev_seq(bus)]) & MCF_FRM_SZ_16BIT) ==
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MCF_FRM_SZ_16BIT) ? 16 : 8;
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setbits_be32(&dspi->ctar[dev_seq(bus)], bus_setup);
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return 0;
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}
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static int coldfire_spi_probe(struct udevice *bus)
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{
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struct coldfire_spi_plat *plat = dev_get_plat(bus);
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struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
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struct dspi *dspi = cfspi->regs;
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int i;
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cfspi->regs = (struct dspi *)plat->regs_addr;
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cfspi->baudrate = plat->speed_hz;
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cfspi->mode = plat->mode;
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for (i = 0; i < MCF_DSPI_MAX_CTAR_REGS; i++) {
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unsigned int ctar = 0;
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if (plat->ctar[i][0] == 0)
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break;
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ctar = DSPI_CTAR_TRSZ(plat->ctar[i][0]) |
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DSPI_CTAR_PCSSCK(plat->ctar[i][1]) |
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DSPI_CTAR_PASC(plat->ctar[i][2]) |
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DSPI_CTAR_PDT(plat->ctar[i][3]) |
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DSPI_CTAR_CSSCK(plat->ctar[i][4]) |
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DSPI_CTAR_ASC(plat->ctar[i][5]) |
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DSPI_CTAR_DT(plat->ctar[i][6]) |
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DSPI_CTAR_BR(plat->ctar[i][7]);
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writel(ctar, &cfspi->regs->ctar[i]);
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}
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/* Default CTARs */
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for (i = 0; i < MCF_DSPI_MAX_CTAR_REGS; i++)
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writel(MCF_DSPI_DEFAULT_CTAR, &dspi->ctar[i]);
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dspi->mcr = DSPI_MCR_MSTR | DSPI_MCR_CSIS7 | DSPI_MCR_CSIS6 |
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DSPI_MCR_CSIS5 | DSPI_MCR_CSIS4 | DSPI_MCR_CSIS3 |
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DSPI_MCR_CSIS2 | DSPI_MCR_CSIS1 | DSPI_MCR_CSIS0 |
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DSPI_MCR_CRXF | DSPI_MCR_CTXF;
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return 0;
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}
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#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
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static int coldfire_dspi_of_to_plat(struct udevice *bus)
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{
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fdt_addr_t addr;
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struct coldfire_spi_plat *plat = dev_get_plat(bus);
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const void *blob = gd->fdt_blob;
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int node = dev_of_offset(bus);
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int *ctar, len;
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addr = dev_read_addr(bus);
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if (addr == FDT_ADDR_T_NONE)
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return -ENOMEM;
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plat->regs_addr = addr;
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plat->num_cs = fdtdec_get_int(blob, node, "num-cs",
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MCF_DSPI_DEFAULT_MAX_CS);
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plat->speed_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
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MCF_DSPI_DEFAULT_SCK_FREQ);
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plat->mode = fdtdec_get_int(blob, node, "spi-mode",
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MCF_DSPI_DEFAULT_MODE);
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memset(plat->ctar, 0, sizeof(plat->ctar));
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ctar = (int *)fdt_getprop(blob, node, "ctar-params", &len);
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if (ctar && len) {
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int i, q, ctar_regs;
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ctar_regs = len / sizeof(unsigned int) / MAX_CTAR_FIELDS;
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if (ctar_regs > MAX_CTAR_REGS)
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ctar_regs = MAX_CTAR_REGS;
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for (i = 0; i < ctar_regs; i++) {
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for (q = 0; q < MAX_CTAR_FIELDS; q++)
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plat->ctar[i][q] = *ctar++;
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}
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}
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debug("DSPI: regs=%pa, max-frequency=%d, num-cs=%d, mode=%d\n",
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(void *)plat->regs_addr,
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plat->speed_hz, plat->num_cs, plat->mode);
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return 0;
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}
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static const struct udevice_id coldfire_spi_ids[] = {
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{ .compatible = "fsl,mcf-dspi" },
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{ }
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};
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#endif
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static const struct dm_spi_ops coldfire_spi_ops = {
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.claim_bus = coldfire_spi_claim_bus,
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.release_bus = coldfire_spi_release_bus,
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.xfer = coldfire_spi_xfer,
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.set_speed = coldfire_spi_set_speed,
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.set_mode = coldfire_spi_set_mode,
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};
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U_BOOT_DRIVER(coldfire_spi) = {
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.name = "spi_coldfire",
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.id = UCLASS_SPI,
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#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
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.of_match = coldfire_spi_ids,
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.of_to_plat = coldfire_dspi_of_to_plat,
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.plat_auto = sizeof(struct coldfire_spi_plat),
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#endif
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.probe = coldfire_spi_probe,
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.ops = &coldfire_spi_ops,
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.priv_auto = sizeof(struct coldfire_spi_priv),
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};
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