179 lines
4.2 KiB
ArmAsm
179 lines
4.2 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2004, Psyent Corporation <www.psyent.com>
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* Scott McNutt <smcnutt@psyent.com>
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*/
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#include <asm-offsets.h>
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#include <config.h>
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/*
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* icache and dcache configuration used only for start.S.
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* the values are chosen so that it will work for all configuration.
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*/
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#define ICACHE_LINE_SIZE 32 /* fixed 32 */
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#define ICACHE_SIZE_MAX 0x10000 /* 64k max */
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#define DCACHE_LINE_SIZE_MIN 4 /* 4, 16, 32 */
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#define DCACHE_SIZE_MAX 0x10000 /* 64k max */
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/* RESTART */
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.text
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.global _start, _except_start, _except_end
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_start:
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wrctl status, r0 /* Disable interrupts */
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/*
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* ICACHE INIT -- only the icache line at the reset address
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* is invalidated at reset. So the init must stay within
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* the cache line size (8 words). If GERMS is used, we'll
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* just be invalidating the cache a second time. If cache
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* is not implemented initi behaves as nop.
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*/
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ori r4, r0, %lo(ICACHE_LINE_SIZE)
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movhi r5, %hi(ICACHE_SIZE_MAX)
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ori r5, r5, %lo(ICACHE_SIZE_MAX)
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0: initi r5
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sub r5, r5, r4
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bgt r5, r0, 0b
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br _except_end /* Skip the tramp */
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/*
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* EXCEPTION TRAMPOLINE -- the following gets copied
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* to the exception address (below), but is otherwise at the
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* default exception vector offset (0x0020).
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*/
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_except_start:
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movhi et, %hi(_exception)
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ori et, et, %lo(_exception)
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jmp et
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_except_end:
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/*
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* INTERRUPTS -- for now, all interrupts masked and globally
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* disabled.
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*/
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wrctl ienable, r0 /* All disabled */
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/*
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* DCACHE INIT -- if dcache not implemented, initd behaves as
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* nop.
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*/
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ori r4, r0, %lo(DCACHE_LINE_SIZE_MIN)
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movhi r5, %hi(DCACHE_SIZE_MAX)
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ori r5, r5, %lo(DCACHE_SIZE_MAX)
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mov r6, r0
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1: initd 0(r6)
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add r6, r6, r4
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bltu r6, r5, 1b
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/*
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* RELOCATE CODE, DATA & COMMAND TABLE -- the following code
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* assumes code, data and the command table are all
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* contiguous. This lets us relocate everything as a single
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* block. Make sure the linker script matches this ;-)
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*/
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nextpc r4
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_cur: movhi r5, %hi(_cur - _start)
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ori r5, r5, %lo(_cur - _start)
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sub r4, r4, r5 /* r4 <- cur _start */
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mov r8, r4
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movhi r5, %hi(_start)
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ori r5, r5, %lo(_start) /* r5 <- linked _start */
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mov sp, r5 /* initial stack below u-boot code */
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beq r4, r5, 3f
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movhi r6, %hi(CONFIG_SYS_MONITOR_LEN)
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ori r6, r6, %lo(CONFIG_SYS_MONITOR_LEN)
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add r6, r6, r5
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2: ldwio r7, 0(r4)
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addi r4, r4, 4
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stwio r7, 0(r5)
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addi r5, r5, 4
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bne r5, r6, 2b
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3:
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/* JUMP TO RELOC ADDR */
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movhi r4, %hi(_reloc)
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ori r4, r4, %lo(_reloc)
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jmp r4
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_reloc:
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/* STACK INIT -- zero top two words for call back chain. */
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addi sp, sp, -8
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stw r0, 0(sp)
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stw r0, 4(sp)
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mov fp, sp
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#ifdef CONFIG_DEBUG_UART
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/* Set up the debug UART */
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movhi r2, %hi(debug_uart_init@h)
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ori r2, r2, %lo(debug_uart_init@h)
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callr r2
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#endif
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/* Allocate and initialize reserved area, update SP */
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mov r4, sp
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movhi r2, %hi(board_init_f_alloc_reserve@h)
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ori r2, r2, %lo(board_init_f_alloc_reserve@h)
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callr r2
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mov sp, r2
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mov r4, sp
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movhi r2, %hi(board_init_f_init_reserve@h)
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ori r2, r2, %lo(board_init_f_init_reserve@h)
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callr r2
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/* Update frame-pointer */
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mov fp, sp
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/* Call board_init_f -- never returns */
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mov r4, r0
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movhi r2, %hi(board_init_f@h)
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ori r2, r2, %lo(board_init_f@h)
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callr r2
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/*
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* NEVER RETURNS -- but branch to the _start just
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* in case ;-)
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*/
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br _start
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/*
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* relocate_code -- Nios2 handles the relocation above. But
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* the generic board code monkeys with the heap, stack, etc.
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* (it makes some assumptions that may not be appropriate
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* for Nios). Nevertheless, we capitulate here.
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*
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* We'll call the board_init_r from here since this isn't
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* supposed to return.
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*
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* void relocate_code(ulong sp, gd_t *global_data,
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* ulong reloc_addr)
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* __attribute__ ((noreturn));
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*/
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.text
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.global relocate_code
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relocate_code:
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mov sp, r4 /* Set the new sp */
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mov r4, r5
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/*
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* ZERO BSS/SBSS -- bss and sbss are assumed to be adjacent
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* and between __bss_start and __bss_end.
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*/
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movhi r5, %hi(__bss_start)
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ori r5, r5, %lo(__bss_start)
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movhi r6, %hi(__bss_end)
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ori r6, r6, %lo(__bss_end)
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beq r5, r6, 5f
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4: stw r0, 0(r5)
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addi r5, r5, 4
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bne r5, r6, 4b
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5:
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movhi r8, %hi(board_init_r@h)
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ori r8, r8, %lo(board_init_r@h)
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callr r8
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ret
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