83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
192 lines
4.4 KiB
C
192 lines
4.4 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2016, NVIDIA CORPORATION.
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <dm.h>
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#include <mailbox-uclass.h>
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#include <dt-bindings/mailbox/tegra186-hsp.h>
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#define TEGRA_HSP_INT_DIMENSIONING 0x380
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#define TEGRA_HSP_INT_DIMENSIONING_NSI_SHIFT 16
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#define TEGRA_HSP_INT_DIMENSIONING_NSI_MASK 0xf
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#define TEGRA_HSP_INT_DIMENSIONING_NDB_SHIFT 12
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#define TEGRA_HSP_INT_DIMENSIONING_NDB_MASK 0xf
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#define TEGRA_HSP_INT_DIMENSIONING_NAS_SHIFT 8
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#define TEGRA_HSP_INT_DIMENSIONING_NAS_MASK 0xf
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#define TEGRA_HSP_INT_DIMENSIONING_NSS_SHIFT 4
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#define TEGRA_HSP_INT_DIMENSIONING_NSS_MASK 0xf
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#define TEGRA_HSP_INT_DIMENSIONING_NSM_SHIFT 0
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#define TEGRA_HSP_INT_DIMENSIONING_NSM_MASK 0xf
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#define TEGRA_HSP_DB_REG_TRIGGER 0x0
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#define TEGRA_HSP_DB_REG_ENABLE 0x4
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#define TEGRA_HSP_DB_REG_RAW 0x8
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#define TEGRA_HSP_DB_REG_PENDING 0xc
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#define TEGRA_HSP_DB_ID_CCPLEX 1
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#define TEGRA_HSP_DB_ID_BPMP 3
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#define TEGRA_HSP_DB_ID_NUM 7
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struct tegra_hsp {
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fdt_addr_t regs;
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uint32_t db_base;
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};
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static uint32_t *tegra_hsp_reg(struct tegra_hsp *thsp, uint32_t db_id,
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uint32_t reg)
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{
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return (uint32_t *)(thsp->regs + thsp->db_base + (db_id * 0x100) + reg);
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}
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static uint32_t tegra_hsp_readl(struct tegra_hsp *thsp, uint32_t db_id,
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uint32_t reg)
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{
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uint32_t *r = tegra_hsp_reg(thsp, db_id, reg);
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return readl(r);
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}
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static void tegra_hsp_writel(struct tegra_hsp *thsp, uint32_t val,
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uint32_t db_id, uint32_t reg)
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{
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uint32_t *r = tegra_hsp_reg(thsp, db_id, reg);
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writel(val, r);
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readl(r);
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}
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static int tegra_hsp_db_id(ulong chan_id)
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{
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switch (chan_id) {
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case (HSP_MBOX_TYPE_DB << 16) | HSP_DB_MASTER_BPMP:
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return TEGRA_HSP_DB_ID_BPMP;
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default:
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debug("Invalid channel ID\n");
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return -EINVAL;
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}
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}
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static int tegra_hsp_of_xlate(struct mbox_chan *chan,
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struct ofnode_phandle_args *args)
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{
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debug("%s(chan=%p)\n", __func__, chan);
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if (args->args_count != 2) {
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debug("Invaild args_count: %d\n", args->args_count);
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return -EINVAL;
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}
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chan->id = (args->args[0] << 16) | args->args[1];
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return 0;
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}
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static int tegra_hsp_request(struct mbox_chan *chan)
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{
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int db_id;
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debug("%s(chan=%p)\n", __func__, chan);
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db_id = tegra_hsp_db_id(chan->id);
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if (db_id < 0) {
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debug("tegra_hsp_db_id() failed: %d\n", db_id);
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return -EINVAL;
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}
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return 0;
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}
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static int tegra_hsp_free(struct mbox_chan *chan)
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{
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debug("%s(chan=%p)\n", __func__, chan);
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return 0;
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}
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static int tegra_hsp_send(struct mbox_chan *chan, const void *data)
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{
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struct tegra_hsp *thsp = dev_get_priv(chan->dev);
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int db_id;
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debug("%s(chan=%p, data=%p)\n", __func__, chan, data);
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db_id = tegra_hsp_db_id(chan->id);
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tegra_hsp_writel(thsp, 1, db_id, TEGRA_HSP_DB_REG_TRIGGER);
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return 0;
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}
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static int tegra_hsp_recv(struct mbox_chan *chan, void *data)
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{
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struct tegra_hsp *thsp = dev_get_priv(chan->dev);
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uint32_t db_id = TEGRA_HSP_DB_ID_CCPLEX;
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uint32_t val;
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debug("%s(chan=%p, data=%p)\n", __func__, chan, data);
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val = tegra_hsp_readl(thsp, db_id, TEGRA_HSP_DB_REG_RAW);
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if (!(val & BIT(chan->id)))
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return -ENODATA;
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tegra_hsp_writel(thsp, BIT(chan->id), db_id, TEGRA_HSP_DB_REG_RAW);
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return 0;
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}
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static int tegra_hsp_bind(struct udevice *dev)
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{
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debug("%s(dev=%p)\n", __func__, dev);
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return 0;
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}
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static int tegra_hsp_probe(struct udevice *dev)
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{
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struct tegra_hsp *thsp = dev_get_priv(dev);
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u32 val;
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int nr_sm, nr_ss, nr_as;
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debug("%s(dev=%p)\n", __func__, dev);
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thsp->regs = devfdt_get_addr(dev);
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if (thsp->regs == FDT_ADDR_T_NONE)
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return -ENODEV;
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val = readl(thsp->regs + TEGRA_HSP_INT_DIMENSIONING);
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nr_sm = (val >> TEGRA_HSP_INT_DIMENSIONING_NSM_SHIFT) &
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TEGRA_HSP_INT_DIMENSIONING_NSM_MASK;
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nr_ss = (val >> TEGRA_HSP_INT_DIMENSIONING_NSS_SHIFT) &
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TEGRA_HSP_INT_DIMENSIONING_NSS_MASK;
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nr_as = (val >> TEGRA_HSP_INT_DIMENSIONING_NAS_SHIFT) &
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TEGRA_HSP_INT_DIMENSIONING_NAS_MASK;
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thsp->db_base = (1 + (nr_sm >> 1) + nr_ss + nr_as) << 16;
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return 0;
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}
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static const struct udevice_id tegra_hsp_ids[] = {
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{ .compatible = "nvidia,tegra186-hsp" },
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{ }
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};
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struct mbox_ops tegra_hsp_mbox_ops = {
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.of_xlate = tegra_hsp_of_xlate,
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.request = tegra_hsp_request,
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.free = tegra_hsp_free,
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.send = tegra_hsp_send,
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.recv = tegra_hsp_recv,
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};
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U_BOOT_DRIVER(tegra_hsp) = {
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.name = "tegra-hsp",
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.id = UCLASS_MAILBOX,
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.of_match = tegra_hsp_ids,
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.bind = tegra_hsp_bind,
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.probe = tegra_hsp_probe,
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.priv_auto_alloc_size = sizeof(struct tegra_hsp),
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.ops = &tegra_hsp_mbox_ops,
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};
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