216800acf1
Conflicts: arch/arm/dts/armada-385-amc.dts arch/arm/dts/armada-xp-theadorable.dts arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi Signed-off-by: Tom Rini <trini@konsulko.com>
151 lines
2.4 KiB
Plaintext
151 lines
2.4 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2018 Microsemi Corporation
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*/
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/dts-v1/;
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#include "mscc,jr2.dtsi"
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#include <dt-bindings/mscc/jr2_data.h>
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/ {
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model = "Jaguar2 Cu8-Sfp16 PCB110 Reference Board";
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compatible = "mscc,jr2-pcb110", "mscc,jr2";
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aliases {
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spi0 = &spi0;
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serial0 = &uart0;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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gpio-leds {
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compatible = "gpio-leds";
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status_green {
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label = "pcb110:green:status";
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gpios = <&gpio 12 0>;
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default-state = "on";
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};
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status_red {
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label = "pcb110:red:status";
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gpios = <&gpio 13 0>;
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default-state = "off";
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};
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};
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};
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&uart0 {
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status = "okay";
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};
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&spi0 {
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status = "okay";
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spi-flash@0 {
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compatible = "jedec,spi-nor";
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spi-max-frequency = <18000000>; /* input clock */
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reg = <0>; /* CS0 */
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};
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};
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&gpio {
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/* SPIO only use DO, CLK, no inputs */
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sgpio1_pins: sgpio1-pins {
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pins = "GPIO_4", "GPIO_5";
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function = "sg1";
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};
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};
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&sgpio {
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status = "okay";
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sgpio-ports = <0x00ffffff>;
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};
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&sgpio1 {
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status = "okay";
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sgpio-ports = <0x00ff0000>;
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};
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&sgpio2 {
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status = "okay";
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sgpio-ports = <0x3f00ffff>;
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gpio-ranges = <&sgpio2 0 0 96>;
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};
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&mdio1 {
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status = "okay";
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phy0: ethernet-phy@0 {
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reg = <0>;
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};
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phy1: ethernet-phy@1 {
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reg = <1>;
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};
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phy2: ethernet-phy@2 {
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reg = <2>;
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};
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phy3: ethernet-phy@3 {
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reg = <3>;
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};
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phy4: ethernet-phy@4 {
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reg = <4>;
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};
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phy5: ethernet-phy@5 {
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reg = <5>;
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};
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phy6: ethernet-phy@6 {
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reg = <6>;
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};
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phy7: ethernet-phy@7 {
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reg = <7>;
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};
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};
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&switch {
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ethernet-ports {
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port0: port@0 {
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reg = <0>;
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phy-handle = <&phy0>;
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phys = <&serdes_hsio 0 SERDES1G(1) PHY_MODE_SGMII>;
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};
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port1: port@1 {
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reg = <1>;
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phy-handle = <&phy1>;
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phys = <&serdes_hsio 1 SERDES1G(2) PHY_MODE_SGMII>;
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};
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port2: port@2 {
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reg = <2>;
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phy-handle = <&phy2>;
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phys = <&serdes_hsio 2 SERDES1G(3) PHY_MODE_SGMII>;
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};
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port3: port@3 {
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reg = <3>;
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phy-handle = <&phy3>;
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phys = <&serdes_hsio 3 SERDES1G(4) PHY_MODE_SGMII>;
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};
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port4: port@4 {
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reg = <4>;
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phy-handle = <&phy4>;
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phys = <&serdes_hsio 4 SERDES1G(5) PHY_MODE_SGMII>;
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};
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port5: port@5 {
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reg = <5>;
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phy-handle = <&phy5>;
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phys = <&serdes_hsio 5 SERDES1G(6) PHY_MODE_SGMII>;
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};
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port6: port@6 {
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reg = <6>;
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phy-handle = <&phy6>;
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phys = <&serdes_hsio 6 SERDES1G(7) PHY_MODE_SGMII>;
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};
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port7: port@7 {
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reg = <7>;
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phy-handle = <&phy7>;
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phys = <&serdes_hsio 7 SERDES1G(8) PHY_MODE_SGMII>;
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};
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};
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};
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