2f8a6db5d8
In order to finish moving this symbol to Kconfig for all platforms, we need to do a few more things. First, for all platforms that define this to a function, introduce CONFIG_DYNAMIC_SYS_CLK_FREQ, similar to CONFIG_DYNAMIC_DDR_CLK_FREQ and populate clock_legacy.h. This entails also switching all users from CONFIG_SYS_CLK_FREQ to get_board_sys_clk() and updating a few preprocessor tests. With that done, all platforms that define a value here can be converted to Kconfig, and a fall-back of zero is sufficiently safe to use (and what is used today in cases where code may or may not have this available). Make sure that code which calls this function includes <clock_legacy.h> to get the prototype. Signed-off-by: Tom Rini <trini@konsulko.com>
96 lines
3.0 KiB
C
96 lines
3.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Watchdog driver for the FTWDT010 Watch Dog Driver
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*
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* (c) Copyright 2004 Faraday Technology Corp. (www.faraday-tech.com)
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* Based on sa1100_wdt.c by Oleg Drokin <green@crimea.edu>
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* Based on SoftDog driver by Alan Cox <alan@redhat.com>
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*
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* Copyright (C) 2011 Andes Technology Corporation
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* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
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*
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* 27/11/2004 Initial release, Faraday.
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* 12/01/2011 Port to u-boot, Macpaul Lin.
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*/
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#ifndef __FTWDT010_H
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#define __FTWDT010_H
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#include <clock_legacy.h>
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struct ftwdt010_wdt {
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unsigned int wdcounter; /* Counter Reg - 0x00 */
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unsigned int wdload; /* Counter Auto Reload Reg - 0x04 */
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unsigned int wdrestart; /* Counter Restart Reg - 0x08 */
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unsigned int wdcr; /* Control Reg - 0x0c */
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unsigned int wdstatus; /* Status Reg - 0x10 */
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unsigned int wdclear; /* Timer Clear - 0x14 */
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unsigned int wdintrlen; /* Interrupt Length - 0x18 */
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};
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/*
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* WDLOAD - Counter Auto Reload Register
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* The Auto Reload Register is set to 0x03EF1480 (66Mhz) by default.
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* Which means in a 66MHz system, the period of Watch Dog timer reset is
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* one second.
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*/
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#define FTWDT010_WDLOAD(x) ((x) & 0xffffffff)
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/*
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* WDRESTART - Watch Dog Timer Counter Restart Register
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* If writing 0x5AB9 to WDRESTART register, Watch Dog timer will
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* automatically reload WDLOAD to WDCOUNTER and restart counting.
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*/
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#define FTWDT010_WDRESTART_MAGIC 0x5AB9
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/* WDCR - Watch Dog Timer Control Register */
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#define FTWDT010_WDCR_ENABLE (1 << 0)
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#define FTWDT010_WDCR_RST (1 << 1)
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#define FTWDT010_WDCR_INTR (1 << 2)
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/* FTWDT010_WDCR_EXT bit: Watch Dog Timer External Signal Enable */
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#define FTWDT010_WDCR_EXT (1 << 3)
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/* FTWDT010_WDCR_CLOCK bit: Clock Source: 0: PCLK, 1: EXTCLK.
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* The clock source PCLK cannot be gated when system sleeps, even if
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* WDCLOCK bit is turned on.
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*
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* Faraday's Watch Dog timer can be driven by an external clock. The
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* programmer just needs to write one to WdCR[WdClock] bit.
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*
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* Note: There is a limitation between EXTCLK and PCLK:
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* EXTCLK cycle time / PCLK cycle time > 2.
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* If the system does not need an external clock,
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* just keep WdCR[WdClock] bit in its default value.
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*/
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#define FTWDT010_WDCR_CLOCK (1 << 4)
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/*
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* WDSTATUS - Watch Dog Timer Status Register
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* This bit is set when the counter reaches Zero
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*/
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#define FTWDT010_WDSTATUS(x) ((x) & 0x1)
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/*
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* WDCLEAR - Watch Dog Timer Clear Register
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* Writing one to this register will clear WDSTATUS.
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*/
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#define FTWDT010_WDCLEAR (1 << 0)
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/*
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* WDINTRLEN - Watch Dog Timer Interrupt Length
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* This register controls the duration length of wd_rst, wd_intr and wd_ext.
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* The default value is 0xFF.
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*/
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#define FTWDT010_WDINTRLEN(x) ((x) & 0xff)
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/*
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* Variable timeout should be set in ms.
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* (get_board_sys_clk()/1000) equals 1 ms.
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* WDLOAD = timeout * TIMEOUT_FACTOR.
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*/
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#define FTWDT010_TIMEOUT_FACTOR (get_board_sys_clk() / 1000) /* 1 ms */
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void ftwdt010_wdt_reset(void);
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void ftwdt010_wdt_disable(void);
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#endif /* __FTWDT010_H */
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