4220504767
The 'get_phy_driver' code in 'drivers/net/phy/phy.c' uses the following
method to determine which driver is to be loaded for a particular PHY
module:
list_for_each(entry, &phy_drivers) {
drv = list_entry(entry, struct phy_driver, list);
if ((drv->uid & drv->mask) == (phy_id & drv->mask))
return drv;
}
This means that a drv->mask of 0xfffff0 will return incorrect phy driver
for the logic above, even if the drv->uid is anything other than
something ending with a 0x0.
For e.g. if the RTL8211E drv->uid is 0x1cc915 and drv->mask is 0xffffff
and the RTL8211B drv->uid is 0x1cc910 and drv->mask is 0xffffff0, then
the phy driver selected will always be RTL8211B even though the
underlying phy connected on the board is a 8211E module.
This patch fixes this issue.
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
142 lines
3.2 KiB
C
142 lines
3.2 KiB
C
/*
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* RealTek PHY drivers
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* Copyright 2010-2011 Freescale Semiconductor, Inc.
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* author Andy Fleming
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*/
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#include <config.h>
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#include <common.h>
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#include <phy.h>
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#define PHY_AUTONEGOTIATE_TIMEOUT 5000
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/* RTL8211x PHY Status Register */
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#define MIIM_RTL8211x_PHY_STATUS 0x11
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#define MIIM_RTL8211x_PHYSTAT_SPEED 0xc000
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#define MIIM_RTL8211x_PHYSTAT_GBIT 0x8000
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#define MIIM_RTL8211x_PHYSTAT_100 0x4000
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#define MIIM_RTL8211x_PHYSTAT_DUPLEX 0x2000
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#define MIIM_RTL8211x_PHYSTAT_SPDDONE 0x0800
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#define MIIM_RTL8211x_PHYSTAT_LINK 0x0400
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/* RealTek RTL8211x */
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static int rtl8211x_config(struct phy_device *phydev)
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{
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phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
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genphy_config_aneg(phydev);
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return 0;
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}
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static int rtl8211x_parse_status(struct phy_device *phydev)
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{
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unsigned int speed;
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unsigned int mii_reg;
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mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_STATUS);
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if (!(mii_reg & MIIM_RTL8211x_PHYSTAT_SPDDONE)) {
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int i = 0;
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/* in case of timeout ->link is cleared */
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phydev->link = 1;
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puts("Waiting for PHY realtime link");
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while (!(mii_reg & MIIM_RTL8211x_PHYSTAT_SPDDONE)) {
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/* Timeout reached ? */
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if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
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puts(" TIMEOUT !\n");
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phydev->link = 0;
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break;
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}
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if ((i++ % 1000) == 0)
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putc('.');
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udelay(1000); /* 1 ms */
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mii_reg = phy_read(phydev, MDIO_DEVAD_NONE,
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MIIM_RTL8211x_PHY_STATUS);
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}
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puts(" done\n");
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udelay(500000); /* another 500 ms (results in faster booting) */
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} else {
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if (mii_reg & MIIM_RTL8211x_PHYSTAT_LINK)
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phydev->link = 1;
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else
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phydev->link = 0;
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}
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if (mii_reg & MIIM_RTL8211x_PHYSTAT_DUPLEX)
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phydev->duplex = DUPLEX_FULL;
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else
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phydev->duplex = DUPLEX_HALF;
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speed = (mii_reg & MIIM_RTL8211x_PHYSTAT_SPEED);
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switch (speed) {
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case MIIM_RTL8211x_PHYSTAT_GBIT:
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phydev->speed = SPEED_1000;
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break;
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case MIIM_RTL8211x_PHYSTAT_100:
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phydev->speed = SPEED_100;
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break;
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default:
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phydev->speed = SPEED_10;
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}
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return 0;
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}
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static int rtl8211x_startup(struct phy_device *phydev)
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{
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/* Read the Status (2x to make sure link is right) */
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genphy_update_link(phydev);
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rtl8211x_parse_status(phydev);
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return 0;
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}
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/* Support for RTL8211B PHY */
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static struct phy_driver RTL8211B_driver = {
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.name = "RealTek RTL8211B",
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.uid = 0x1cc910,
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.mask = 0xffffff,
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.features = PHY_GBIT_FEATURES,
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.config = &rtl8211x_config,
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.startup = &rtl8211x_startup,
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.shutdown = &genphy_shutdown,
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};
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/* Support for RTL8211E-VB-CG, RTL8211E-VL-CG and RTL8211EG-VB-CG PHYs */
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static struct phy_driver RTL8211E_driver = {
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.name = "RealTek RTL8211E",
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.uid = 0x1cc915,
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.mask = 0xffffff,
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.features = PHY_GBIT_FEATURES,
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.config = &rtl8211x_config,
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.startup = &rtl8211x_startup,
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.shutdown = &genphy_shutdown,
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};
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/* Support for RTL8211DN PHY */
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static struct phy_driver RTL8211DN_driver = {
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.name = "RealTek RTL8211DN",
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.uid = 0x1cc914,
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.mask = 0xffffff,
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.features = PHY_GBIT_FEATURES,
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.config = &rtl8211x_config,
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.startup = &rtl8211x_startup,
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.shutdown = &genphy_shutdown,
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};
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int phy_realtek_init(void)
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{
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phy_register(&RTL8211B_driver);
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phy_register(&RTL8211E_driver);
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phy_register(&RTL8211DN_driver);
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return 0;
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}
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