d8d33b6d4d
Port for the DART-6UL Evaluation Kit SBC. Based on the variscite DART-6UL iMX6ULL SoM. CPU: Freescale i.MX6ULL rev1.1 900 MHz (running at 396 MHz) CPU: Commercial temperature grade (0C to 95C) at 43C Reset cause: POR Model: Variscite DART-6UL Evaluation Kit Board: Variscite DART-6UL Evaluation Kit DRAM: 512 MiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 In: serial@02020000 Out: serial@02020000 Err: serial@02020000 Net: FEC0 Working: - Eth0 - i2c - MMC/SD - eMMC - USB host - UART 1 Note: LCDIF porting needs DM_VIDEO https://lists.denx.de/pipermail/u-boot/2019-April/365506.html Signed-off-by: Parthiban Nallathambi <parthitce@gmail.com>
262 lines
5.9 KiB
Plaintext
262 lines
5.9 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
|
|
/*
|
|
* Copyright (C) 2019 Parthiban Nallathambi <parthitce@gmail.com>
|
|
*/
|
|
|
|
/ {
|
|
model = "Variscite DART-6UL i.MX6 Ultra Low Lite SOM";
|
|
compatible = "variscite,imx6ull-dart-6ul", "fsl,imx6ull";
|
|
|
|
memory {
|
|
reg = <0x80000000 0x20000000>;
|
|
};
|
|
|
|
chosen {
|
|
stdout-path = &uart1;
|
|
};
|
|
};
|
|
|
|
&fec1 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_enet1>;
|
|
phy-mode = "rmii";
|
|
phy-handle = <ðphy0>;
|
|
status = "okay";
|
|
|
|
mdio1: mdio1 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
ethphy0: ethernet-phy@1 {
|
|
reg = <1>;
|
|
micrel,led-mode = <1>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&fec2 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_enet2>;
|
|
phy-mode = "rmii";
|
|
phy-handle = <ðphy1>;
|
|
status = "okay";
|
|
|
|
mdio2: mdio2 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
ethphy1: ethernet-phy@2 {
|
|
reg = <2>;
|
|
micrel,led-mode = <1>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&gpmi {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_gpmi_nand>;
|
|
nand-on-flash-bbt;
|
|
fsl,no-blockmark-swap;
|
|
status = "disabled";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
partition@0 {
|
|
label = "uboot";
|
|
reg = <0x0 0x400000>;
|
|
};
|
|
|
|
partition@400000 {
|
|
label = "uboot-env";
|
|
reg = <0x400000 0x100000>;
|
|
};
|
|
|
|
partition@500000 {
|
|
label = "root";
|
|
reg = <0x500000 0x0>;
|
|
};
|
|
};
|
|
|
|
&i2c1 {
|
|
clock-frequency = <100000>;
|
|
pinctrl-names = "default", "gpio";
|
|
pinctrl-0 = <&pinctrl_i2c1>;
|
|
pinctrl-1 = <&pinctrl_i2c1_gpio>;
|
|
scl-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
|
|
sda-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
|
|
status = "okay";
|
|
};
|
|
|
|
&i2c2 {
|
|
clock-frequency = <100000>;
|
|
pinctrl-names = "default", "gpio";
|
|
pinctrl-0 = <&pinctrl_i2c2>;
|
|
pinctrl-1 = <&pinctrl_i2c2_gpio>;
|
|
scl-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
|
|
sda-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>;
|
|
status = "okay";
|
|
|
|
eeprom@50 {
|
|
compatible = "cat,24c32";
|
|
reg = <0x50>;
|
|
};
|
|
};
|
|
|
|
&pwm1 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_pwm1>;
|
|
#pwm-cells = <3>;
|
|
status = "okay";
|
|
};
|
|
|
|
&uart1 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_uart1>;
|
|
status = "okay";
|
|
};
|
|
|
|
&usdhc1 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_usdhc1>;
|
|
cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
|
|
bus-width = <0x4>;
|
|
no-1-8-v;
|
|
status = "okay";
|
|
};
|
|
|
|
&usdhc2 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_usdhc2>;
|
|
bus-width = <8>;
|
|
no-1-8-v;
|
|
non-removable;
|
|
keep-power-in-suspend;
|
|
status = "disabled";
|
|
};
|
|
|
|
&iomuxc {
|
|
pinctrl-names = "default";
|
|
|
|
pinctrl_enet1: enet1grp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
|
|
MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0X1b0b0
|
|
MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
|
|
MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
|
|
MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
|
|
MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
|
|
MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
|
|
MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
|
|
MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
|
|
MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
|
|
>;
|
|
};
|
|
|
|
pinctrl_enet2: enet2grp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
|
|
MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0X1b0b0
|
|
MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
|
|
MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
|
|
MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
|
|
MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
|
|
MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
|
|
MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
|
|
MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
|
|
MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
|
|
>;
|
|
};
|
|
|
|
pinctrl_gpmi_nand: gpminandgrp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_NAND_DQS__RAWNAND_DQS 0x0b0b1
|
|
MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1
|
|
MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1
|
|
MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1
|
|
MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000
|
|
MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1
|
|
MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0x0b0b1
|
|
MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1
|
|
MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1
|
|
MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1
|
|
MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1
|
|
MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1
|
|
MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1
|
|
MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1
|
|
MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1
|
|
MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1
|
|
MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c1: i2cgrp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
|
|
MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c1_gpio: i2c1grp_gpio {
|
|
fsl,pins = <
|
|
MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x1b8b0
|
|
MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x1b8b0
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c2: i2cgrp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
|
|
MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c2_gpio: i2c2grp_gpio {
|
|
fsl,pins = <
|
|
MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b8b0
|
|
MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x1b8b0
|
|
>;
|
|
};
|
|
|
|
pinctrl_pwm1: pwm1grp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0x1b0b1
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart1: uart1grp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
|
|
MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc1: usdhc1grp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
|
|
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
|
|
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
|
|
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
|
|
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
|
|
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
|
|
MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059
|
|
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc2: usdhc2grp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
|
|
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
|
|
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
|
|
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
|
|
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
|
|
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
|
|
MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9
|
|
MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9
|
|
MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9
|
|
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9
|
|
>;
|
|
};
|
|
};
|