35b65dd8ef
Historically, the reset_cpu() function had an `addr` parameter which was
meant to pass in an address of the reset vector location, where the CPU
should reset to. This feature is no longer used anywhere in U-Boot as
all reset_cpu() implementations now ignore the passed value. Generic
code has been added which always calls reset_cpu() with `0` which means
this feature can no longer be used easily anyway.
Over time, many implementations seem to have "misunderstood" the
existence of this parameter as a way to customize/parameterize the reset
(e.g. COLD vs WARM resets). As this is not properly supported, the
code will almost always not do what it is intended to (because all
call-sites just call reset_cpu() with 0).
To avoid confusion and to clean up the codebase from unused left-overs
of the past, remove the `addr` parameter entirely. Code which intends
to support different kinds of resets should be rewritten as a sysreset
driver instead.
This transformation was done with the following coccinelle patch:
@@
expression argvalue;
@@
- reset_cpu(argvalue)
+ reset_cpu()
@@
identifier argname;
type argtype;
@@
- reset_cpu(argtype argname)
+ reset_cpu(void)
{ ... }
Signed-off-by: Harald Seiler <hws@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
146 lines
2.9 KiB
C
146 lines
2.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2012 Michal Simek <monstr@monstr.eu>
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* Copyright (C) 2012 Xilinx, Inc. All rights reserved.
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*/
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#include <common.h>
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#include <cpu_func.h>
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#include <init.h>
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#include <zynqpl.h>
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#include <asm/cache.h>
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#include <asm/io.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/ps7_init_gpl.h>
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#include <asm/arch/sys_proto.h>
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#define ZYNQ_SILICON_VER_MASK 0xF0000000
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#define ZYNQ_SILICON_VER_SHIFT 28
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#if CONFIG_IS_ENABLED(FPGA)
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xilinx_desc fpga = {
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.family = xilinx_zynq,
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.iface = devcfg,
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.operations = &zynq_op,
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};
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#endif
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static const struct {
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u8 idcode;
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#if defined(CONFIG_FPGA)
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u32 fpga_size;
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#endif
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char *devicename;
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} zynq_fpga_descs[] = {
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ZYNQ_DESC(7Z007S),
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ZYNQ_DESC(7Z010),
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ZYNQ_DESC(7Z012S),
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ZYNQ_DESC(7Z014S),
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ZYNQ_DESC(7Z015),
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ZYNQ_DESC(7Z020),
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ZYNQ_DESC(7Z030),
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ZYNQ_DESC(7Z035),
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ZYNQ_DESC(7Z045),
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ZYNQ_DESC(7Z100),
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{ /* Sentinel */ },
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};
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int arch_cpu_init(void)
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{
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zynq_slcr_unlock();
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#ifndef CONFIG_SPL_BUILD
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/* Device config APB, unlock the PCAP */
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writel(0x757BDF0D, &devcfg_base->unlock);
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writel(0xFFFFFFFF, &devcfg_base->rom_shadow);
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#if (CONFIG_SYS_SDRAM_BASE == 0)
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/* remap DDR to zero, FILTERSTART */
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writel(0, &scu_base->filter_start);
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/* OCM_CFG, Mask out the ROM, map ram into upper addresses */
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writel(0x1F, &slcr_base->ocm_cfg);
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/* FPGA_RST_CTRL, clear resets on AXI fabric ports */
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writel(0x0, &slcr_base->fpga_rst_ctrl);
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/* Set urgent bits with register */
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writel(0x0, &slcr_base->ddr_urgent_sel);
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/* Urgent write, ports S2/S3 */
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writel(0xC, &slcr_base->ddr_urgent);
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#endif
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#endif
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zynq_slcr_lock();
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return 0;
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}
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unsigned int zynq_get_silicon_version(void)
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{
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return (readl(&devcfg_base->mctrl) & ZYNQ_SILICON_VER_MASK)
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>> ZYNQ_SILICON_VER_SHIFT;
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}
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void reset_cpu(void)
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{
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zynq_slcr_cpu_reset();
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while (1)
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;
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}
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#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
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void enable_caches(void)
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{
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/* Enable D-cache. I-cache is already enabled in start.S */
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dcache_enable();
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}
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#endif
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static int __maybe_unused cpu_desc_id(void)
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{
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u32 idcode;
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u8 i;
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idcode = zynq_slcr_get_idcode();
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for (i = 0; zynq_fpga_descs[i].idcode; i++) {
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if (zynq_fpga_descs[i].idcode == idcode)
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return i;
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}
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return -ENODEV;
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}
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#if defined(CONFIG_ARCH_EARLY_INIT_R)
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int arch_early_init_r(void)
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{
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#if CONFIG_IS_ENABLED(FPGA)
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int cpu_id = cpu_desc_id();
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if (cpu_id < 0)
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return 0;
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fpga.size = zynq_fpga_descs[cpu_id].fpga_size;
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fpga.name = zynq_fpga_descs[cpu_id].devicename;
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fpga_init();
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fpga_add(fpga_xilinx, &fpga);
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#endif
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return 0;
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}
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#endif
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#ifdef CONFIG_DISPLAY_CPUINFO
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int print_cpuinfo(void)
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{
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u32 version;
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int cpu_id = cpu_desc_id();
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if (cpu_id < 0)
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return 0;
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version = zynq_get_silicon_version() << 1;
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if (version > (PCW_SILICON_VERSION_3 << 1))
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version += 1;
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printf("CPU: Zynq %s\n", zynq_fpga_descs[cpu_id].devicename);
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printf("Silicon: v%d.%d\n", version >> 1, version & 1);
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return 0;
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}
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#endif
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