Previously, SPD configuration of RAM was non functional on
this board. Now that the root cause is known (an i2c address
conflict), there is a simple end-user workaround - remove the
old slower local bus 128MB module and then SPD detection on the
main DDR2 memory module works fine.
We make the enablement of the LBC SDRAM support conditional on
being not SPD enabled. We can revisit this dependency as the
hardware workaround becomes available.
Turning off LBC SDRAM support revealed a couple implict dependencies
in the tlb/law code that always expected an LBC SDRAM address.
This has been tested with the default 256MB module, a 512MB
a 1GB and a 2GB, of varying speeds, and the SPD autoconfiguration
worked fine in all cases.
The default configuration remains to go with the hard coded
DDR config, so the default build will continue to work on boards
where people don't bother to read the docs. But the advantage
of going to the SPD config is that even the small default module
gets configured for CL3 instead of CL4.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Storage of the board specific values (ethaddr...)
-------------------------------------------------
The board specific environment variables that should be unique
for each individual board, can be stored in the I2C EEPROM. This
will be done from offset 0x80 with the length of 0x80 bytes. The
following command can be used to store the values here:
=> setdef de:20:6a:ed:e2:72 de:20:6a:ed:e2:73 AB0001
ethaddr eth1addr serial#
Now those 3 values are stored into the I2C EEPROM. A CRC is added
to make sure that the values get not corrupted.
SW-Reset Pushbutton handling:
-----------------------------
The SW-reset push button is connected to a GPIO input too. This
way U-Boot can "see" how long the SW-reset was pressed, and a
specific action can be taken. Two different actions are supported:
a) Release after more than 5 seconds and less then 10 seconds:
-> Run POST
Please note, that the POST test will take a while (approx. 1 min
on the 128MByte board). This is mainly due to the system memory
test.
b) Release after more than 10 seconds:
-> Restore factory default settings
The factory default values are restored. The default environment
variables are restored (ipaddr, serverip...) and the board
specific values (ethaddr, eth1addr and serial#) are restored
to the environment from the I2C EEPROM. Also a bootline parameter
is added to the Linux bootline to signal the Linux kernel upon
the next startup, that the factory defaults should be restored.
The command to check this sw-reset status and act accordingly is
=> chkreset
This command is added to the default "bootcmd", so that it is called
automatically upon startup.
Also, the 2 LED's are used to indicate the current status of this
command (time passed since pushing the button). When the POST test
will be run, the green LED will be switched off, and when the
factory restore will be initiated, the reg LED will be switched off.
Loggin of POST results:
-----------------------
The results of the POST tests are logged in a logbuffer located at the end
of the onboard memory. It can be accessed with the U-Boot command "log":
=> log show
<4>POST memory PASSED
<4>POST cache PASSED
<4>POST cpu PASSED
<4>POST uart PASSED
<4>POST ethernet PASSED
The DENX Linux kernel tree has support for this log buffer included. Exactly
this buffer is used for logging of all kernel messages too. By enabling the
compile time option "CONFIG_LOGBUFFER" this support is enabled. This way you
can access the U-Boot log messages from Linux too.
2007-08-10, Stefan Roese <sr@denx.de>
7e44f2b710