c978b52410
The Xtensa processor architecture is a configurable, extensible, and synthesizable 32-bit RISC processor core provided by Tensilica, inc. This is the second part of the basic architecture port, adding the 'arch/xtensa' directory and a readme file. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
19 lines
189 B
Plaintext
19 lines
189 B
Plaintext
menu "Xtensa architecture"
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depends on XTENSA
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config SYS_ARCH
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string
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default "xtensa"
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config SYS_CPU
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string "Xtensa Core Variant"
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choice
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prompt "Target select"
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endchoice
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endmenu
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