Bryan Brattlof 10c8bafbc3 soc: soc_ti_k3: identify j7200 SR2.0 SoCs ... Anytime a new revision of a chip is produced, Texas Instruments will increment the 4 bit VARIANT section of the CTRLMMR_WKUP_JTAGID register by one. Typically this will be decoded as SR1.0 -> SR2.0 ... however a few TI SoCs do not follow this convention. Rather than defining a revision string array for each SoC, use a default revision string array for all TI SoCs that continue to follow the typical 1.0 -> 2.0 revision scheme. Signed-off-by: Bryan Brattlof <bb@ti.com>		2022-07-06 14:30:51 -04:00
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ti	soc: ti: pruss: Add a platform driver for PRUSS in TI SoCs	2021-07-15 17:56:04 +05:30
Kconfig	soc: xilinx: versal: Add soc_xilinx_versal driver	2021-08-26 08:08:11 +02:00
Makefile	soc: xilinx: versal: Add soc_xilinx_versal driver	2021-08-26 08:08:11 +02:00
soc_sandbox.c	test: Add tests for SOC uclass	2020-07-25 14:46:57 -06:00
soc_ti_k3.c	soc: soc_ti_k3: identify j7200 SR2.0 SoCs	2022-07-06 14:30:51 -04:00
soc_xilinx_versal.c	soc: xilinx: versal: fix out of bounds array access	2022-05-13 09:10:02 +02:00
soc_xilinx_zynqmp.c	soc: xilinx: zynqmp: Add machine identification support	2022-06-24 14:37:27 +02:00
soc-uclass.c	dm: define LOG_CATEGORY for all uclass	2021-07-06 10:38:03 -06:00