95954f55e9
Double Transfer Rate (DTR) is SPI protocol in which data is transferred on each clock edge as opposed to on each clock cycle. Make framework-level changes to allow supporting flashes in DTR mode. Right now, mixed DTR modes are not supported. So, for example a mode like 4S-4D-4D will not work. All phases need to be either DTR or STR. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
98 lines
2.8 KiB
C
98 lines
2.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* SPI flash internal definitions
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*
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* Copyright (C) 2008 Atmel Corporation
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* Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
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*/
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#ifndef _SF_INTERNAL_H_
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#define _SF_INTERNAL_H_
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#include <linux/bitops.h>
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#include <linux/types.h>
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#include <linux/compiler.h>
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#define SPI_NOR_MAX_ID_LEN 6
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#define SPI_NOR_MAX_ADDR_WIDTH 4
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struct flash_info {
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#if !CONFIG_IS_ENABLED(SPI_FLASH_TINY)
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char *name;
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#endif
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/*
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* This array stores the ID bytes.
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* The first three bytes are the JEDIC ID.
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* JEDEC ID zero means "no ID" (mostly older chips).
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*/
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u8 id[SPI_NOR_MAX_ID_LEN];
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u8 id_len;
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/* The size listed here is what works with SPINOR_OP_SE, which isn't
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* necessarily called a "sector" by the vendor.
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*/
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unsigned int sector_size;
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u16 n_sectors;
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u16 page_size;
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u16 addr_width;
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u32 flags;
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#define SECT_4K BIT(0) /* SPINOR_OP_BE_4K works uniformly */
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#define SPI_NOR_NO_ERASE BIT(1) /* No erase command needed */
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#define SST_WRITE BIT(2) /* use SST byte programming */
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#define SPI_NOR_NO_FR BIT(3) /* Can't do fastread */
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#define SECT_4K_PMC BIT(4) /* SPINOR_OP_BE_4K_PMC works uniformly */
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#define SPI_NOR_DUAL_READ BIT(5) /* Flash supports Dual Read */
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#define SPI_NOR_QUAD_READ BIT(6) /* Flash supports Quad Read */
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#define USE_FSR BIT(7) /* use flag status register */
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#define SPI_NOR_HAS_LOCK BIT(8) /* Flash supports lock/unlock via SR */
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#define SPI_NOR_HAS_TB BIT(9) /*
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* Flash SR has Top/Bottom (TB) protect
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* bit. Must be used with
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* SPI_NOR_HAS_LOCK.
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*/
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#define SPI_S3AN BIT(10) /*
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* Xilinx Spartan 3AN In-System Flash
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* (MFR cannot be used for probing
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* because it has the same value as
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* ATMEL flashes)
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*/
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#define SPI_NOR_4B_OPCODES BIT(11) /*
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* Use dedicated 4byte address op codes
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* to support memory size above 128Mib.
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*/
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#define NO_CHIP_ERASE BIT(12) /* Chip does not support chip erase */
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#define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */
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#define USE_CLSR BIT(14) /* use CLSR command */
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#define SPI_NOR_HAS_SST26LOCK BIT(15) /* Flash supports lock/unlock via BPR */
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#define SPI_NOR_OCTAL_READ BIT(16) /* Flash supports Octal Read */
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#define SPI_NOR_OCTAL_DTR_READ BIT(17) /* Flash supports Octal DTR Read */
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};
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extern const struct flash_info spi_nor_ids[];
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#define JEDEC_MFR(info) ((info)->id[0])
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#define JEDEC_ID(info) (((info)->id[1]) << 8 | ((info)->id[2]))
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/* Get software write-protect value (BP bits) */
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int spi_flash_cmd_get_sw_write_prot(struct spi_flash *flash);
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#if CONFIG_IS_ENABLED(SPI_FLASH_MTD)
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int spi_flash_mtd_register(struct spi_flash *flash);
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void spi_flash_mtd_unregister(struct spi_flash *flash);
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#else
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static inline int spi_flash_mtd_register(struct spi_flash *flash)
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{
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return 0;
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}
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static inline void spi_flash_mtd_unregister(struct spi_flash *flash)
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{
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}
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#endif
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#endif /* _SF_INTERNAL_H_ */
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