168 lines
5.2 KiB
C
168 lines
5.2 KiB
C
/*
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* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* PCI Configuration space access support
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*/
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#include <common.h>
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#include <pci.h>
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#include <asm/io.h>
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#include <asm/immap.h>
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#if defined(CONFIG_PCI)
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/* System RAM mapped over PCI */
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#define CONFIG_SYS_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE
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#define CONFIG_SYS_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE
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#define CONFIG_SYS_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
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#define cfg_read(val, addr, type, op) *val = op((type)(addr));
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#define cfg_write(val, addr, type, op) op((type *)(addr), (val));
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#define PCI_OP(rw, size, type, op, mask) \
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int pci_##rw##_cfg_##size(struct pci_controller *hose, \
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pci_dev_t dev, int offset, type val) \
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{ \
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u32 addr = 0; \
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u16 cfg_type = 0; \
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addr = ((offset & 0xfc) | cfg_type | (dev) | 0x80000000); \
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out_be32(hose->cfg_addr, addr); \
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cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \
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__asm__ __volatile__("nop"); \
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__asm__ __volatile__("nop"); \
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out_be32(hose->cfg_addr, addr & 0x7fffffff); \
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return 0; \
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}
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PCI_OP(read, byte, u8 *, in_8, 3)
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PCI_OP(read, word, u16 *, in_le16, 2)
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PCI_OP(write, byte, u8, out_8, 3)
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PCI_OP(write, word, u16, out_le16, 2)
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PCI_OP(write, dword, u32, out_le32, 0)
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int pci_read_cfg_dword(struct pci_controller *hose, pci_dev_t dev,
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int offset, u32 * val)
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{
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u32 addr;
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u32 tmpv;
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u32 mask = 2; /* word access */
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/* Read lower 16 bits */
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addr = ((offset & 0xfc) | (dev) | 0x80000000);
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out_be32(hose->cfg_addr, addr);
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*val = (u32) in_le16((u16 *) (hose->cfg_data + (offset & mask)));
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__asm__ __volatile__("nop");
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out_be32(hose->cfg_addr, addr & 0x7fffffff);
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/* Read upper 16 bits */
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offset += 2;
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addr = ((offset & 0xfc) | 1 | (dev) | 0x80000000);
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out_be32(hose->cfg_addr, addr);
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tmpv = (u32) in_le16((u16 *) (hose->cfg_data + (offset & mask)));
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__asm__ __volatile__("nop");
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out_be32(hose->cfg_addr, addr & 0x7fffffff);
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/* combine results into dword value */
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*val = (tmpv << 16) | *val;
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return 0;
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}
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void pci_mcf547x_8x_init(struct pci_controller *hose)
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{
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volatile pci_t *pci = (volatile pci_t *) MMAP_PCI;
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volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
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/* Port configuration */
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gpio->par_pcibg =
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GPIO_PAR_PCIBG_PCIBG0(3) | GPIO_PAR_PCIBG_PCIBG1(3) |
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GPIO_PAR_PCIBG_PCIBG2(3) | GPIO_PAR_PCIBG_PCIBG3(3) |
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GPIO_PAR_PCIBG_PCIBG4(3);
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gpio->par_pcibr =
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GPIO_PAR_PCIBR_PCIBR0(3) | GPIO_PAR_PCIBR_PCIBR1(3) |
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GPIO_PAR_PCIBR_PCIBR2(3) | GPIO_PAR_PCIBR_PCIBR3(3) |
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GPIO_PAR_PCIBR_PCIBR4(3);
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/* Assert reset bit */
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pci->gscr |= PCI_GSCR_PR;
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pci->tcr1 = PCI_TCR1_P;
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/* Initiator windows */
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pci->iw0btar = CONFIG_SYS_PCI_MEM_PHYS | (CONFIG_SYS_PCI_MEM_PHYS >> 16);
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pci->iw1btar = CONFIG_SYS_PCI_IO_PHYS | (CONFIG_SYS_PCI_IO_PHYS >> 16);
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pci->iw2btar = CONFIG_SYS_PCI_CFG_PHYS | (CONFIG_SYS_PCI_CFG_PHYS >> 16);
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pci->iwcr =
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PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO |
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PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO;
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pci->icr = 0;
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/* Enable bus master and mem access */
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pci->scr = PCI_SCR_B | PCI_SCR_M;
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/* Cache line size and master latency */
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pci->cr1 = PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xF8);
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pci->cr2 = 0;
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#ifdef CONFIG_SYS_PCI_BAR0
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pci->bar0 = PCI_BAR_BAR0(CONFIG_SYS_PCI_BAR0);
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pci->tbatr0a = CONFIG_SYS_PCI_TBATR0 | PCI_TBATR_EN;
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#endif
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#ifdef CONFIG_SYS_PCI_BAR1
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pci->bar1 = PCI_BAR_BAR1(CONFIG_SYS_PCI_BAR1);
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pci->tbatr1a = CONFIG_SYS_PCI_TBATR1 | PCI_TBATR_EN;
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#endif
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/* Deassert reset bit */
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pci->gscr &= ~PCI_GSCR_PR;
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udelay(1000);
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/* Enable PCI bus master support */
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hose->first_busno = 0;
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hose->last_busno = 0xff;
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pci_set_region(hose->regions + 0, CONFIG_SYS_PCI_MEM_BUS, CONFIG_SYS_PCI_MEM_PHYS,
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CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM);
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pci_set_region(hose->regions + 1, CONFIG_SYS_PCI_IO_BUS, CONFIG_SYS_PCI_IO_PHYS,
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CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO);
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pci_set_region(hose->regions + 2, CONFIG_SYS_PCI_SYS_MEM_BUS,
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CONFIG_SYS_PCI_SYS_MEM_PHYS, CONFIG_SYS_PCI_SYS_MEM_SIZE,
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PCI_REGION_MEM | PCI_REGION_MEMORY);
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hose->region_count = 3;
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hose->cfg_addr = &(pci->car);
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hose->cfg_data = (volatile unsigned char *)CONFIG_SYS_PCI_CFG_BUS;
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pci_set_ops(hose, pci_read_cfg_byte, pci_read_cfg_word,
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pci_read_cfg_dword, pci_write_cfg_byte, pci_write_cfg_word,
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pci_write_cfg_dword);
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/* Hose scan */
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pci_register_hose(hose);
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hose->last_busno = pci_hose_scan(hose);
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}
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#endif /* CONFIG_PCI */
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