01964d8e23
On STM32 family, the IPCC peripheral allows the communication between 2 processors offering doorbells mechanism. Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com> Signed-off-by: Loic Pallardy <loic.pallardy@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
168 lines
3.4 KiB
C
168 lines
3.4 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <mailbox-uclass.h>
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#include <asm/io.h>
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/*
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* IPCC has one set of registers per CPU
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* IPCC_PROC_OFFST allows to define cpu registers set base address
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* according to the assigned proc_id.
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*/
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#define IPCC_PROC_OFFST 0x010
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#define IPCC_XSCR 0x008
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#define IPCC_XTOYSR 0x00c
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#define IPCC_HWCFGR 0x3f0
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#define IPCFGR_CHAN_MASK GENMASK(7, 0)
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#define RX_BIT_CHAN(chan) BIT(chan)
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#define TX_BIT_SHIFT 16
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#define TX_BIT_CHAN(chan) BIT(TX_BIT_SHIFT + (chan))
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#define STM32_MAX_PROCS 2
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struct stm32_ipcc {
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void __iomem *reg_base;
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void __iomem *reg_proc;
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u32 proc_id;
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u32 n_chans;
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};
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static int stm32_ipcc_request(struct mbox_chan *chan)
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{
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struct stm32_ipcc *ipcc = dev_get_priv(chan->dev);
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debug("%s(chan=%p)\n", __func__, chan);
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if (chan->id >= ipcc->n_chans) {
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debug("%s failed to request channel: %ld\n",
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__func__, chan->id);
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return -EINVAL;
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}
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return 0;
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}
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static int stm32_ipcc_free(struct mbox_chan *chan)
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{
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debug("%s(chan=%p)\n", __func__, chan);
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return 0;
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}
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static int stm32_ipcc_send(struct mbox_chan *chan, const void *data)
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{
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struct stm32_ipcc *ipcc = dev_get_priv(chan->dev);
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debug("%s(chan=%p, data=%p)\n", __func__, chan, data);
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if (readl(ipcc->reg_proc + IPCC_XTOYSR) & BIT(chan->id))
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return -EBUSY;
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/* set channel n occupied */
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setbits_le32(ipcc->reg_proc + IPCC_XSCR, TX_BIT_CHAN(chan->id));
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return 0;
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}
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static int stm32_ipcc_recv(struct mbox_chan *chan, void *data)
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{
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struct stm32_ipcc *ipcc = dev_get_priv(chan->dev);
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u32 val;
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int proc_offset;
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debug("%s(chan=%p, data=%p)\n", __func__, chan, data);
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/* read 'channel occupied' status from other proc */
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proc_offset = ipcc->proc_id ? -IPCC_PROC_OFFST : IPCC_PROC_OFFST;
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val = readl(ipcc->reg_proc + proc_offset + IPCC_XTOYSR);
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if (!(val & BIT(chan->id)))
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return -ENODATA;
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setbits_le32(ipcc->reg_proc + IPCC_XSCR, RX_BIT_CHAN(chan->id));
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return 0;
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}
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static int stm32_ipcc_probe(struct udevice *dev)
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{
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struct stm32_ipcc *ipcc = dev_get_priv(dev);
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fdt_addr_t addr;
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const fdt32_t *cell;
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struct clk clk;
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int len, ret;
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debug("%s(dev=%p)\n", __func__, dev);
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addr = dev_read_addr(dev);
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if (addr == FDT_ADDR_T_NONE)
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return -EINVAL;
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ipcc->reg_base = (void __iomem *)addr;
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/* proc_id */
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cell = dev_read_prop(dev, "st,proc_id", &len);
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if (len < sizeof(fdt32_t)) {
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dev_dbg(dev, "Missing st,proc_id\n");
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return -EINVAL;
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}
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ipcc->proc_id = fdtdec_get_number(cell, 1);
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if (ipcc->proc_id >= STM32_MAX_PROCS) {
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dev_err(dev, "Invalid proc_id (%d)\n", ipcc->proc_id);
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return -EINVAL;
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}
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ipcc->reg_proc = ipcc->reg_base + ipcc->proc_id * IPCC_PROC_OFFST;
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ret = clk_get_by_index(dev, 0, &clk);
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if (ret)
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return ret;
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ret = clk_enable(&clk);
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if (ret)
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goto clk_free;
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/* get channel number */
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ipcc->n_chans = readl(ipcc->reg_base + IPCC_HWCFGR);
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ipcc->n_chans &= IPCFGR_CHAN_MASK;
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return 0;
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clk_free:
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clk_free(&clk);
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return ret;
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}
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static const struct udevice_id stm32_ipcc_ids[] = {
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{ .compatible = "st,stm32mp1-ipcc" },
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{ }
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};
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struct mbox_ops stm32_ipcc_mbox_ops = {
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.request = stm32_ipcc_request,
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.free = stm32_ipcc_free,
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.send = stm32_ipcc_send,
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.recv = stm32_ipcc_recv,
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};
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U_BOOT_DRIVER(stm32_ipcc) = {
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.name = "stm32_ipcc",
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.id = UCLASS_MAILBOX,
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.of_match = stm32_ipcc_ids,
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.probe = stm32_ipcc_probe,
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.priv_auto_alloc_size = sizeof(struct stm32_ipcc),
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.ops = &stm32_ipcc_mbox_ops,
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};
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