Lukas Auer 2503ccc55f riscv: delay initialization of caches and debug UART ... Move the initialization of the caches and the debug UART until after board_init_f_init_reserve. This is in preparation for SMP support, where code prior to this point will be executed by all harts. This ensures that initialization will only be performed once on the main hart running U-Boot. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>		2019-04-08 09:44:26 +08:00
..
cpu	riscv: delay initialization of caches and debug UART	2019-04-08 09:44:26 +08:00
dts	riscv: Remove ae350.dts	2018-12-18 09:56:27 +08:00
include/asm	riscv: import the supervisor binary interface header file	2019-04-08 09:44:25 +08:00
lib	riscv: implement IPI platform functions using SBI	2019-04-08 09:44:26 +08:00
config.mk	riscv: qemu: define standalone load address	2019-01-15 09:36:31 +08:00
Kconfig	riscv: implement IPI platform functions using SBI	2019-04-08 09:44:26 +08:00
Makefile	riscv: add Kconfig entries for the code model	2018-12-18 09:56:26 +08:00