09aac75e4d
This is an improved version of the driver patch original
submitted by Graeme Smecher <graeme.smecher@mail.mcgill.ca>
The changes are:
- remove hard coded Xilinx BSP defines (XPAR_SPI_*) and
use CONFIG_SYS_SPI_BASE from config.h instead
- add extensive register struct definitions
- remove offset calculation for register access and
use the new register struct instead
- move default SPI controller configuration from
spi_setup_slave() to spi_claim_bus()
- add spi_set_speed()
- insert SPI controller deactivation in spi_release_bus()
- protect while loops in spi_xfer() with counter / timeouts
- support SPI mode flags: LSB_FIRST, CPHA, CPOL, LOOP
Come from:
http://patchwork.ozlabs.org/patch/71797/
Signed-off-by: Stephan Linz <linz@li-pro.net>
Tested-by: Michal Simek <monstr@monstr.eu>
136 lines
4.1 KiB
C
136 lines
4.1 KiB
C
/*
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* Xilinx SPI driver
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*
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* XPS/AXI bus interface
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*
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* based on bfin_spi.c, by way of altera_spi.c
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* Copyright (c) 2005-2008 Analog Devices Inc.
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* Copyright (c) 2010 Thomas Chou <thomas@wytron.com.tw>
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* Copyright (c) 2010 Graeme Smecher <graeme.smecher@mail.mcgill.ca>
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* Copyright (c) 2012 Stephan Linz <linz@li-pro.net>
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*
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* Licensed under the GPL-2 or later.
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*
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* [0]: http://www.xilinx.com/support/documentation
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*
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* [S]: [0]/ip_documentation/xps_spi.pdf
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* [0]/ip_documentation/axi_spi_ds742.pdf
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*/
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#ifndef _XILINX_SPI_
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#define _XILINX_SPI_
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#include <asm/types.h>
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#include <asm/io.h>
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/*
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* Xilinx SPI Register Definition
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*
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* [1]: [0]/ip_documentation/xps_spi.pdf
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* page 8, Register Descriptions
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* [2]: [0]/ip_documentation/axi_spi_ds742.pdf
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* page 7, Register Overview Table
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*/
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struct xilinx_spi_reg {
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u32 __space0__[7];
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u32 dgier; /* Device Global Interrupt Enable Register (DGIER) */
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u32 ipisr; /* IP Interrupt Status Register (IPISR) */
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u32 __space1__;
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u32 ipier; /* IP Interrupt Enable Register (IPIER) */
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u32 __space2__[5];
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u32 srr; /* Softare Reset Register (SRR) */
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u32 __space3__[7];
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u32 spicr; /* SPI Control Register (SPICR) */
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u32 spisr; /* SPI Status Register (SPISR) */
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u32 spidtr; /* SPI Data Transmit Register (SPIDTR) */
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u32 spidrr; /* SPI Data Receive Register (SPIDRR) */
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u32 spissr; /* SPI Slave Select Register (SPISSR) */
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u32 spitfor; /* SPI Transmit FIFO Occupancy Register (SPITFOR) */
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u32 spirfor; /* SPI Receive FIFO Occupancy Register (SPIRFOR) */
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};
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/* Device Global Interrupt Enable Register (dgier), [1] p15, [2] p15 */
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#define DGIER_GIE (1 << 31)
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/* IP Interrupt Status Register (ipisr), [1] p15, [2] p15 */
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#define IPISR_DRR_NOT_EMPTY (1 << 8)
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#define IPISR_SLAVE_SELECT (1 << 7)
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#define IPISR_TXF_HALF_EMPTY (1 << 6)
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#define IPISR_DRR_OVERRUN (1 << 5)
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#define IPISR_DRR_FULL (1 << 4)
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#define IPISR_DTR_UNDERRUN (1 << 3)
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#define IPISR_DTR_EMPTY (1 << 2)
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#define IPISR_SLAVE_MODF (1 << 1)
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#define IPISR_MODF (1 << 0)
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/* IP Interrupt Enable Register (ipier), [1] p17, [2] p18 */
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#define IPIER_DRR_NOT_EMPTY (1 << 8)
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#define IPIER_SLAVE_SELECT (1 << 7)
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#define IPIER_TXF_HALF_EMPTY (1 << 6)
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#define IPIER_DRR_OVERRUN (1 << 5)
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#define IPIER_DRR_FULL (1 << 4)
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#define IPIER_DTR_UNDERRUN (1 << 3)
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#define IPIER_DTR_EMPTY (1 << 2)
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#define IPIER_SLAVE_MODF (1 << 1)
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#define IPIER_MODF (1 << 0)
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/* Softare Reset Register (srr), [1] p9, [2] p8 */
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#define SRR_RESET_CODE 0x0000000A
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/* SPI Control Register (spicr), [1] p9, [2] p8 */
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#define SPICR_LSB_FIRST (1 << 9)
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#define SPICR_MASTER_INHIBIT (1 << 8)
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#define SPICR_MANUAL_SS (1 << 7)
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#define SPICR_RXFIFO_RESEST (1 << 6)
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#define SPICR_TXFIFO_RESEST (1 << 5)
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#define SPICR_CPHA (1 << 4)
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#define SPICR_CPOL (1 << 3)
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#define SPICR_MASTER_MODE (1 << 2)
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#define SPICR_SPE (1 << 1)
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#define SPICR_LOOP (1 << 0)
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/* SPI Status Register (spisr), [1] p11, [2] p10 */
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#define SPISR_SLAVE_MODE_SELECT (1 << 5)
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#define SPISR_MODF (1 << 4)
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#define SPISR_TX_FULL (1 << 3)
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#define SPISR_TX_EMPTY (1 << 2)
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#define SPISR_RX_FULL (1 << 1)
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#define SPISR_RX_EMPTY (1 << 0)
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/* SPI Data Transmit Register (spidtr), [1] p12, [2] p12 */
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#define SPIDTR_8BIT_MASK (0xff << 0)
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#define SPIDTR_16BIT_MASK (0xffff << 0)
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#define SPIDTR_32BIT_MASK (0xffffffff << 0)
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/* SPI Data Receive Register (spidrr), [1] p12, [2] p12 */
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#define SPIDRR_8BIT_MASK (0xff << 0)
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#define SPIDRR_16BIT_MASK (0xffff << 0)
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#define SPIDRR_32BIT_MASK (0xffffffff << 0)
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/* SPI Slave Select Register (spissr), [1] p13, [2] p13 */
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#define SPISSR_MASK(cs) (1 << (cs))
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#define SPISSR_ACT(cs) ~SPISSR_MASK(cs)
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#define SPISSR_OFF ~0UL
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/* SPI Transmit FIFO Occupancy Register (spitfor), [1] p13, [2] p14 */
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#define SPITFOR_OCYVAL_POS 0
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#define SPITFOR_OCYVAL_MASK (0xf << SPITFOR_OCYVAL_POS)
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/* SPI Receive FIFO Occupancy Register (spirfor), [1] p14, [2] p14 */
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#define SPIRFOR_OCYVAL_POS 0
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#define SPIRFOR_OCYVAL_MASK (0xf << SPIRFOR_OCYVAL_POS)
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struct xilinx_spi_slave {
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struct spi_slave slave;
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struct xilinx_spi_reg *regs;
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unsigned int freq;
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unsigned int mode;
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};
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static inline struct xilinx_spi_slave *to_xilinx_spi_slave(
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struct spi_slave *slave)
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{
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return container_of(slave, struct xilinx_spi_slave, slave);
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}
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#endif /* _XILINX_SPI_ */
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