ad734f7dc2
This board is still a non-generic board. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
1018 lines
24 KiB
C
1018 lines
24 KiB
C
/*
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* (C) Copyright 2003-2010
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* This file is based on mpc4200fec.c,
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* (C) Copyright Motorola, Inc., 2000
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*/
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#include <common.h>
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#include <mpc5xxx.h>
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#include <mpc5xxx_sdma.h>
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#include <malloc.h>
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#include <net.h>
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#include <netdev.h>
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#include <miiphy.h>
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#include "mpc5xxx_fec.h"
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DECLARE_GLOBAL_DATA_PTR;
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/* #define DEBUG 0x28 */
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#if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
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#error "CONFIG_MII has to be defined!"
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#endif
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#if (DEBUG & 0x60)
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static void tfifo_print(char *devname, mpc5xxx_fec_priv *fec);
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static void rfifo_print(char *devname, mpc5xxx_fec_priv *fec);
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#endif /* DEBUG */
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typedef struct {
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uint8 data[1500]; /* actual data */
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int length; /* actual length */
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int used; /* buffer in use or not */
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uint8 head[16]; /* MAC header(6 + 6 + 2) + 2(aligned) */
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} NBUF;
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int fec5xxx_miiphy_read(const char *devname, uint8 phyAddr, uint8 regAddr, uint16 *retVal);
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int fec5xxx_miiphy_write(const char *devname, uint8 phyAddr, uint8 regAddr, uint16 data);
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static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis);
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/********************************************************************/
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#if (DEBUG & 0x2)
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static void mpc5xxx_fec_phydump (char *devname)
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{
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uint16 phyStatus, i;
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uint8 phyAddr = CONFIG_PHY_ADDR;
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uint8 reg_mask[] = {
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#if CONFIG_PHY_TYPE == 0x79c874 /* AMD Am79C874 */
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/* regs to print: 0...7, 16...19, 21, 23, 24 */
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1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0,
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1, 1, 1, 1, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0,
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#else
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/* regs to print: 0...8, 16...20 */
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1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0,
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1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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#endif
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};
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for (i = 0; i < 32; i++) {
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if (reg_mask[i]) {
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miiphy_read(devname, phyAddr, i, &phyStatus);
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printf("Mii reg %d: 0x%04x\n", i, phyStatus);
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}
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}
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}
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#endif
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/********************************************************************/
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static int mpc5xxx_fec_rbd_init(mpc5xxx_fec_priv *fec)
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{
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int ix;
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char *data;
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static int once = 0;
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for (ix = 0; ix < FEC_RBD_NUM; ix++) {
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if (!once) {
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data = (char *)malloc(FEC_MAX_PKT_SIZE);
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if (data == NULL) {
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printf ("RBD INIT FAILED\n");
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return -1;
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}
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fec->rbdBase[ix].dataPointer = (uint32)data;
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}
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fec->rbdBase[ix].status = FEC_RBD_EMPTY;
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fec->rbdBase[ix].dataLength = 0;
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}
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once ++;
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/*
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* have the last RBD to close the ring
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*/
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fec->rbdBase[ix - 1].status |= FEC_RBD_WRAP;
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fec->rbdIndex = 0;
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return 0;
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}
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/********************************************************************/
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static void mpc5xxx_fec_tbd_init(mpc5xxx_fec_priv *fec)
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{
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int ix;
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for (ix = 0; ix < FEC_TBD_NUM; ix++) {
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fec->tbdBase[ix].status = 0;
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}
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/*
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* Have the last TBD to close the ring
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*/
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fec->tbdBase[ix - 1].status |= FEC_TBD_WRAP;
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/*
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* Initialize some indices
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*/
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fec->tbdIndex = 0;
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fec->usedTbdIndex = 0;
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fec->cleanTbdNum = FEC_TBD_NUM;
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}
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/********************************************************************/
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static void mpc5xxx_fec_rbd_clean(mpc5xxx_fec_priv *fec, volatile FEC_RBD * pRbd)
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{
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/*
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* Reset buffer descriptor as empty
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*/
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if ((fec->rbdIndex) == (FEC_RBD_NUM - 1))
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pRbd->status = (FEC_RBD_WRAP | FEC_RBD_EMPTY);
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else
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pRbd->status = FEC_RBD_EMPTY;
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pRbd->dataLength = 0;
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/*
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* Now, we have an empty RxBD, restart the SmartDMA receive task
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*/
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SDMA_TASK_ENABLE(FEC_RECV_TASK_NO);
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/*
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* Increment BD count
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*/
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fec->rbdIndex = (fec->rbdIndex + 1) % FEC_RBD_NUM;
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}
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/********************************************************************/
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static void mpc5xxx_fec_tbd_scrub(mpc5xxx_fec_priv *fec)
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{
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volatile FEC_TBD *pUsedTbd;
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#if (DEBUG & 0x1)
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printf ("tbd_scrub: fec->cleanTbdNum = %d, fec->usedTbdIndex = %d\n",
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fec->cleanTbdNum, fec->usedTbdIndex);
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#endif
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/*
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* process all the consumed TBDs
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*/
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while (fec->cleanTbdNum < FEC_TBD_NUM) {
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pUsedTbd = &fec->tbdBase[fec->usedTbdIndex];
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if (pUsedTbd->status & FEC_TBD_READY) {
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#if (DEBUG & 0x20)
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printf("Cannot clean TBD %d, in use\n", fec->cleanTbdNum);
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#endif
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return;
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}
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/*
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* clean this buffer descriptor
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*/
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if (fec->usedTbdIndex == (FEC_TBD_NUM - 1))
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pUsedTbd->status = FEC_TBD_WRAP;
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else
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pUsedTbd->status = 0;
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/*
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* update some indeces for a correct handling of the TBD ring
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*/
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fec->cleanTbdNum++;
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fec->usedTbdIndex = (fec->usedTbdIndex + 1) % FEC_TBD_NUM;
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}
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}
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/********************************************************************/
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static void mpc5xxx_fec_set_hwaddr(mpc5xxx_fec_priv *fec, char *mac)
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{
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uint8 currByte; /* byte for which to compute the CRC */
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int byte; /* loop - counter */
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int bit; /* loop - counter */
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uint32 crc = 0xffffffff; /* initial value */
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/*
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* The algorithm used is the following:
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* we loop on each of the six bytes of the provided address,
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* and we compute the CRC by left-shifting the previous
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* value by one position, so that each bit in the current
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* byte of the address may contribute the calculation. If
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* the latter and the MSB in the CRC are different, then
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* the CRC value so computed is also ex-ored with the
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* "polynomium generator". The current byte of the address
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* is also shifted right by one bit at each iteration.
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* This is because the CRC generatore in hardware is implemented
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* as a shift-register with as many ex-ores as the radixes
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* in the polynomium. This suggests that we represent the
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* polynomiumm itself as a 32-bit constant.
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*/
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for (byte = 0; byte < 6; byte++) {
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currByte = mac[byte];
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for (bit = 0; bit < 8; bit++) {
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if ((currByte & 0x01) ^ (crc & 0x01)) {
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crc >>= 1;
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crc = crc ^ 0xedb88320;
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} else {
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crc >>= 1;
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}
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currByte >>= 1;
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}
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}
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crc = crc >> 26;
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/*
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* Set individual hash table register
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*/
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if (crc >= 32) {
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fec->eth->iaddr1 = (1 << (crc - 32));
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fec->eth->iaddr2 = 0;
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} else {
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fec->eth->iaddr1 = 0;
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fec->eth->iaddr2 = (1 << crc);
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}
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/*
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* Set physical address
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*/
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fec->eth->paddr1 = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3];
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fec->eth->paddr2 = (mac[4] << 24) + (mac[5] << 16) + 0x8808;
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}
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/********************************************************************/
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static int mpc5xxx_fec_init(struct eth_device *dev, bd_t * bis)
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{
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mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
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struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA;
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#if (DEBUG & 0x1)
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printf ("mpc5xxx_fec_init... Begin\n");
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#endif
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mpc5xxx_fec_init_phy(dev, bis);
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/*
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* Call board-specific PHY fixups (if any)
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*/
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#ifdef CONFIG_RESET_PHY_R
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reset_phy();
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#endif
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/*
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* Initialize RxBD/TxBD rings
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*/
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mpc5xxx_fec_rbd_init(fec);
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mpc5xxx_fec_tbd_init(fec);
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/*
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* Clear FEC-Lite interrupt event register(IEVENT)
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*/
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fec->eth->ievent = 0xffffffff;
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/*
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* Set interrupt mask register
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*/
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fec->eth->imask = 0x00000000;
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/*
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* Set FEC-Lite receive control register(R_CNTRL):
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*/
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if (fec->xcv_type == SEVENWIRE) {
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/*
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* Frame length=1518; 7-wire mode
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*/
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fec->eth->r_cntrl = 0x05ee0020; /*0x05ee0000;FIXME */
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} else {
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/*
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* Frame length=1518; MII mode;
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*/
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fec->eth->r_cntrl = 0x05ee0024; /*0x05ee0004;FIXME */
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}
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fec->eth->x_cntrl = 0x00000000; /* half-duplex, heartbeat disabled */
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/*
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* Set Opcode/Pause Duration Register
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*/
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fec->eth->op_pause = 0x00010020; /*FIXME 0xffff0020; */
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/*
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* Set Rx FIFO alarm and granularity value
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*/
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fec->eth->rfifo_cntrl = 0x0c000000
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| (fec->eth->rfifo_cntrl & ~0x0f000000);
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fec->eth->rfifo_alarm = 0x0000030c;
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#if (DEBUG & 0x22)
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if (fec->eth->rfifo_status & 0x00700000 ) {
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printf("mpc5xxx_fec_init() RFIFO error\n");
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}
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#endif
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/*
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* Set Tx FIFO granularity value
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*/
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fec->eth->tfifo_cntrl = 0x0c000000
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| (fec->eth->tfifo_cntrl & ~0x0f000000);
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#if (DEBUG & 0x2)
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printf("tfifo_status: 0x%08x\n", fec->eth->tfifo_status);
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printf("tfifo_alarm: 0x%08x\n", fec->eth->tfifo_alarm);
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#endif
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/*
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* Set transmit fifo watermark register(X_WMRK), default = 64
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*/
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fec->eth->tfifo_alarm = 0x00000080;
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fec->eth->x_wmrk = 0x2;
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/*
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* Set individual address filter for unicast address
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* and set physical address registers.
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*/
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mpc5xxx_fec_set_hwaddr(fec, (char *)dev->enetaddr);
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/*
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* Set multicast address filter
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*/
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fec->eth->gaddr1 = 0x00000000;
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fec->eth->gaddr2 = 0x00000000;
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/*
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* Turn ON cheater FSM: ????
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*/
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fec->eth->xmit_fsm = 0x03000000;
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/*
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* Turn off COMM bus prefetch in the MPC5200 BestComm. It doesn't
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* work w/ the current receive task.
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*/
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sdma->PtdCntrl |= 0x00000001;
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/*
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* Set priority of different initiators
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*/
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sdma->IPR0 = 7; /* always */
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sdma->IPR3 = 6; /* Eth RX */
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sdma->IPR4 = 5; /* Eth Tx */
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/*
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* Clear SmartDMA task interrupt pending bits
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*/
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SDMA_CLEAR_IEVENT(FEC_RECV_TASK_NO);
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/*
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* Initialize SmartDMA parameters stored in SRAM
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*/
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*(volatile int *)FEC_TBD_BASE = (int)fec->tbdBase;
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*(volatile int *)FEC_RBD_BASE = (int)fec->rbdBase;
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*(volatile int *)FEC_TBD_NEXT = (int)fec->tbdBase;
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*(volatile int *)FEC_RBD_NEXT = (int)fec->rbdBase;
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/*
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* Enable FEC-Lite controller
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*/
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fec->eth->ecntrl |= 0x00000006;
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#if (DEBUG & 0x2)
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if (fec->xcv_type != SEVENWIRE)
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mpc5xxx_fec_phydump (dev->name);
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#endif
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/*
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* Enable SmartDMA receive task
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*/
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SDMA_TASK_ENABLE(FEC_RECV_TASK_NO);
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#if (DEBUG & 0x1)
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printf("mpc5xxx_fec_init... Done \n");
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#endif
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return 1;
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}
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/********************************************************************/
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static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis)
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{
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mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
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const uint8 phyAddr = CONFIG_PHY_ADDR; /* Only one PHY */
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static int initialized = 0;
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if(initialized)
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return 0;
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initialized = 1;
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#if (DEBUG & 0x1)
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printf ("mpc5xxx_fec_init_phy... Begin\n");
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#endif
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/*
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* Initialize GPIO pins
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*/
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if (fec->xcv_type == SEVENWIRE) {
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/* 10MBit with 7-wire operation */
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/* 7-wire only */
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*(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00020000;
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} else {
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/* 100MBit with MD operation */
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*(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00050000;
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}
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/*
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* Clear FEC-Lite interrupt event register(IEVENT)
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*/
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fec->eth->ievent = 0xffffffff;
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/*
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* Set interrupt mask register
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*/
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fec->eth->imask = 0x00000000;
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/*
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* In original Promess-provided code PHY initialization is disabled with the
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* following comment: "Phy initialization is DISABLED for now. There was a
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* problem with running 100 Mbps on PRO board". Thus we temporarily disable
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* PHY initialization for the Motion-PRO board, until a proper fix is found.
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*/
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if (fec->xcv_type != SEVENWIRE) {
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/*
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* Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
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* and do not drop the Preamble.
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* No MII for 7-wire mode
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*/
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fec->eth->mii_speed = (((gd->arch.ipb_clk >> 20) / 5) << 1);
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}
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if (fec->xcv_type != SEVENWIRE) {
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/*
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* Initialize PHY(LXT971A):
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*
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* Generally, on power up, the LXT971A reads its configuration
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* pins to check for forced operation, If not cofigured for
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* forced operation, it uses auto-negotiation/parallel detection
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* to automatically determine line operating conditions.
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* If the PHY device on the other side of the link supports
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* auto-negotiation, the LXT971A auto-negotiates with it
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* using Fast Link Pulse(FLP) Bursts. If the PHY partner does not
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* support auto-negotiation, the LXT971A automatically detects
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* the presence of either link pulses(10Mbps PHY) or Idle
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* symbols(100Mbps) and sets its operating conditions accordingly.
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*
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* When auto-negotiation is controlled by software, the following
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* steps are recommended.
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*
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* Note:
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* The physical address is dependent on hardware configuration.
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*
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*/
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int timeout = 1;
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uint16 phyStatus;
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/*
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* Reset PHY, then delay 300ns
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*/
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miiphy_write(dev->name, phyAddr, 0x0, 0x8000);
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udelay(1000);
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if (fec->xcv_type == MII10) {
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/*
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* Force 10Base-T, FDX operation
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*/
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#if (DEBUG & 0x2)
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printf("Forcing 10 Mbps ethernet link... ");
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#endif
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miiphy_read(dev->name, phyAddr, 0x1, &phyStatus);
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/*
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miiphy_write(dev->name, fec, phyAddr, 0x0, 0x0100);
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*/
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miiphy_write(dev->name, phyAddr, 0x0, 0x0180);
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timeout = 20;
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do { /* wait for link status to go down */
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udelay(10000);
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if ((timeout--) == 0) {
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#if (DEBUG & 0x2)
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printf("hmmm, should not have waited...");
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#endif
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break;
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}
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miiphy_read(dev->name, phyAddr, 0x1, &phyStatus);
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#if (DEBUG & 0x2)
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printf("=");
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#endif
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} while ((phyStatus & 0x0004)); /* !link up */
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timeout = 1000;
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do { /* wait for link status to come back up */
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udelay(10000);
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if ((timeout--) == 0) {
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printf("failed. Link is down.\n");
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break;
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}
|
|
miiphy_read(dev->name, phyAddr, 0x1, &phyStatus);
|
|
#if (DEBUG & 0x2)
|
|
printf("+");
|
|
#endif
|
|
} while (!(phyStatus & 0x0004)); /* !link up */
|
|
|
|
#if (DEBUG & 0x2)
|
|
printf ("done.\n");
|
|
#endif
|
|
} else { /* MII100 */
|
|
/*
|
|
* Set the auto-negotiation advertisement register bits
|
|
*/
|
|
miiphy_write(dev->name, phyAddr, 0x4, 0x01e1);
|
|
|
|
/*
|
|
* Set MDIO bit 0.12 = 1(&& bit 0.9=1?) to enable auto-negotiation
|
|
*/
|
|
miiphy_write(dev->name, phyAddr, 0x0, 0x1200);
|
|
|
|
/*
|
|
* Wait for AN completion
|
|
*/
|
|
timeout = 5000;
|
|
do {
|
|
udelay(1000);
|
|
|
|
if ((timeout--) == 0) {
|
|
#if (DEBUG & 0x2)
|
|
printf("PHY auto neg 0 failed...\n");
|
|
#endif
|
|
return -1;
|
|
}
|
|
|
|
if (miiphy_read(dev->name, phyAddr, 0x1, &phyStatus) != 0) {
|
|
#if (DEBUG & 0x2)
|
|
printf("PHY auto neg 1 failed 0x%04x...\n", phyStatus);
|
|
#endif
|
|
return -1;
|
|
}
|
|
} while (!(phyStatus & 0x0004));
|
|
|
|
#if (DEBUG & 0x2)
|
|
printf("PHY auto neg complete! \n");
|
|
#endif
|
|
}
|
|
|
|
}
|
|
|
|
#if (DEBUG & 0x2)
|
|
if (fec->xcv_type != SEVENWIRE)
|
|
mpc5xxx_fec_phydump (dev->name);
|
|
#endif
|
|
|
|
|
|
#if (DEBUG & 0x1)
|
|
printf("mpc5xxx_fec_init_phy... Done \n");
|
|
#endif
|
|
|
|
return 1;
|
|
}
|
|
|
|
/********************************************************************/
|
|
static void mpc5xxx_fec_halt(struct eth_device *dev)
|
|
{
|
|
struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA;
|
|
mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
|
|
int counter = 0xffff;
|
|
|
|
#if (DEBUG & 0x2)
|
|
if (fec->xcv_type != SEVENWIRE)
|
|
mpc5xxx_fec_phydump (dev->name);
|
|
#endif
|
|
|
|
/*
|
|
* mask FEC chip interrupts
|
|
*/
|
|
fec->eth->imask = 0;
|
|
|
|
/*
|
|
* issue graceful stop command to the FEC transmitter if necessary
|
|
*/
|
|
fec->eth->x_cntrl |= 0x00000001;
|
|
|
|
/*
|
|
* wait for graceful stop to register
|
|
*/
|
|
while ((counter--) && (!(fec->eth->ievent & 0x10000000))) ;
|
|
|
|
/*
|
|
* Disable SmartDMA tasks
|
|
*/
|
|
SDMA_TASK_DISABLE (FEC_XMIT_TASK_NO);
|
|
SDMA_TASK_DISABLE (FEC_RECV_TASK_NO);
|
|
|
|
/*
|
|
* Turn on COMM bus prefetch in the MPC5200 BestComm after we're
|
|
* done. It doesn't work w/ the current receive task.
|
|
*/
|
|
sdma->PtdCntrl &= ~0x00000001;
|
|
|
|
/*
|
|
* Disable the Ethernet Controller
|
|
*/
|
|
fec->eth->ecntrl &= 0xfffffffd;
|
|
|
|
/*
|
|
* Clear FIFO status registers
|
|
*/
|
|
fec->eth->rfifo_status &= 0x00700000;
|
|
fec->eth->tfifo_status &= 0x00700000;
|
|
|
|
fec->eth->reset_cntrl = 0x01000000;
|
|
|
|
/*
|
|
* Issue a reset command to the FEC chip
|
|
*/
|
|
fec->eth->ecntrl |= 0x1;
|
|
|
|
/*
|
|
* wait at least 16 clock cycles
|
|
*/
|
|
udelay(10);
|
|
|
|
/* don't leave the MII speed set to zero */
|
|
if (fec->xcv_type != SEVENWIRE) {
|
|
/*
|
|
* Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
|
|
* and do not drop the Preamble.
|
|
* No MII for 7-wire mode
|
|
*/
|
|
fec->eth->mii_speed = (((gd->arch.ipb_clk >> 20) / 5) << 1);
|
|
}
|
|
|
|
#if (DEBUG & 0x3)
|
|
printf("Ethernet task stopped\n");
|
|
#endif
|
|
}
|
|
|
|
#if (DEBUG & 0x60)
|
|
/********************************************************************/
|
|
|
|
static void tfifo_print(char *devname, mpc5xxx_fec_priv *fec)
|
|
{
|
|
uint16 phyAddr = CONFIG_PHY_ADDR;
|
|
uint16 phyStatus;
|
|
|
|
if ((fec->eth->tfifo_lrf_ptr != fec->eth->tfifo_lwf_ptr)
|
|
|| (fec->eth->tfifo_rdptr != fec->eth->tfifo_wrptr)) {
|
|
|
|
miiphy_read(devname, phyAddr, 0x1, &phyStatus);
|
|
printf("\nphyStatus: 0x%04x\n", phyStatus);
|
|
printf("ecntrl: 0x%08x\n", fec->eth->ecntrl);
|
|
printf("ievent: 0x%08x\n", fec->eth->ievent);
|
|
printf("x_status: 0x%08x\n", fec->eth->x_status);
|
|
printf("tfifo: status 0x%08x\n", fec->eth->tfifo_status);
|
|
|
|
printf(" control 0x%08x\n", fec->eth->tfifo_cntrl);
|
|
printf(" lrfp 0x%08x\n", fec->eth->tfifo_lrf_ptr);
|
|
printf(" lwfp 0x%08x\n", fec->eth->tfifo_lwf_ptr);
|
|
printf(" alarm 0x%08x\n", fec->eth->tfifo_alarm);
|
|
printf(" readptr 0x%08x\n", fec->eth->tfifo_rdptr);
|
|
printf(" writptr 0x%08x\n", fec->eth->tfifo_wrptr);
|
|
}
|
|
}
|
|
|
|
static void rfifo_print(char *devname, mpc5xxx_fec_priv *fec)
|
|
{
|
|
uint16 phyAddr = CONFIG_PHY_ADDR;
|
|
uint16 phyStatus;
|
|
|
|
if ((fec->eth->rfifo_lrf_ptr != fec->eth->rfifo_lwf_ptr)
|
|
|| (fec->eth->rfifo_rdptr != fec->eth->rfifo_wrptr)) {
|
|
|
|
miiphy_read(devname, phyAddr, 0x1, &phyStatus);
|
|
printf("\nphyStatus: 0x%04x\n", phyStatus);
|
|
printf("ecntrl: 0x%08x\n", fec->eth->ecntrl);
|
|
printf("ievent: 0x%08x\n", fec->eth->ievent);
|
|
printf("x_status: 0x%08x\n", fec->eth->x_status);
|
|
printf("rfifo: status 0x%08x\n", fec->eth->rfifo_status);
|
|
|
|
printf(" control 0x%08x\n", fec->eth->rfifo_cntrl);
|
|
printf(" lrfp 0x%08x\n", fec->eth->rfifo_lrf_ptr);
|
|
printf(" lwfp 0x%08x\n", fec->eth->rfifo_lwf_ptr);
|
|
printf(" alarm 0x%08x\n", fec->eth->rfifo_alarm);
|
|
printf(" readptr 0x%08x\n", fec->eth->rfifo_rdptr);
|
|
printf(" writptr 0x%08x\n", fec->eth->rfifo_wrptr);
|
|
}
|
|
}
|
|
#endif /* DEBUG */
|
|
|
|
/********************************************************************/
|
|
|
|
static int mpc5xxx_fec_send(struct eth_device *dev, void *eth_data,
|
|
int data_length)
|
|
{
|
|
/*
|
|
* This routine transmits one frame. This routine only accepts
|
|
* 6-byte Ethernet addresses.
|
|
*/
|
|
mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
|
|
volatile FEC_TBD *pTbd;
|
|
|
|
#if (DEBUG & 0x20)
|
|
printf("tbd status: 0x%04x\n", fec->tbdBase[0].status);
|
|
tfifo_print(dev->name, fec);
|
|
#endif
|
|
|
|
/*
|
|
* Clear Tx BD ring at first
|
|
*/
|
|
mpc5xxx_fec_tbd_scrub(fec);
|
|
|
|
/*
|
|
* Check for valid length of data.
|
|
*/
|
|
if ((data_length > 1500) || (data_length <= 0)) {
|
|
return -1;
|
|
}
|
|
|
|
/*
|
|
* Check the number of vacant TxBDs.
|
|
*/
|
|
if (fec->cleanTbdNum < 1) {
|
|
#if (DEBUG & 0x20)
|
|
printf("No available TxBDs ...\n");
|
|
#endif
|
|
return -1;
|
|
}
|
|
|
|
/*
|
|
* Get the first TxBD to send the mac header
|
|
*/
|
|
pTbd = &fec->tbdBase[fec->tbdIndex];
|
|
pTbd->dataLength = data_length;
|
|
pTbd->dataPointer = (uint32)eth_data;
|
|
pTbd->status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
|
|
fec->tbdIndex = (fec->tbdIndex + 1) % FEC_TBD_NUM;
|
|
|
|
#if (DEBUG & 0x100)
|
|
printf("SDMA_TASK_ENABLE, fec->tbdIndex = %d \n", fec->tbdIndex);
|
|
#endif
|
|
|
|
/*
|
|
* Kick the MII i/f
|
|
*/
|
|
if (fec->xcv_type != SEVENWIRE) {
|
|
uint16 phyStatus;
|
|
miiphy_read(dev->name, 0, 0x1, &phyStatus);
|
|
}
|
|
|
|
/*
|
|
* Enable SmartDMA transmit task
|
|
*/
|
|
|
|
#if (DEBUG & 0x20)
|
|
tfifo_print(dev->name, fec);
|
|
#endif
|
|
SDMA_TASK_ENABLE (FEC_XMIT_TASK_NO);
|
|
#if (DEBUG & 0x20)
|
|
tfifo_print(dev->name, fec);
|
|
#endif
|
|
#if (DEBUG & 0x8)
|
|
printf( "+" );
|
|
#endif
|
|
|
|
fec->cleanTbdNum -= 1;
|
|
|
|
#if (DEBUG & 0x129) && (DEBUG & 0x80000000)
|
|
printf ("smartDMA ethernet Tx task enabled\n");
|
|
#endif
|
|
/*
|
|
* wait until frame is sent .
|
|
*/
|
|
while (pTbd->status & FEC_TBD_READY) {
|
|
udelay(10);
|
|
#if (DEBUG & 0x8)
|
|
printf ("TDB status = %04x\n", pTbd->status);
|
|
#endif
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
/********************************************************************/
|
|
static int mpc5xxx_fec_recv(struct eth_device *dev)
|
|
{
|
|
/*
|
|
* This command pulls one frame from the card
|
|
*/
|
|
mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
|
|
volatile FEC_RBD *pRbd = &fec->rbdBase[fec->rbdIndex];
|
|
unsigned long ievent;
|
|
int frame_length, len = 0;
|
|
NBUF *frame;
|
|
uchar buff[FEC_MAX_PKT_SIZE];
|
|
|
|
#if (DEBUG & 0x1)
|
|
printf ("mpc5xxx_fec_recv %d Start...\n", fec->rbdIndex);
|
|
#endif
|
|
#if (DEBUG & 0x8)
|
|
printf( "-" );
|
|
#endif
|
|
|
|
/*
|
|
* Check if any critical events have happened
|
|
*/
|
|
ievent = fec->eth->ievent;
|
|
fec->eth->ievent = ievent;
|
|
if (ievent & 0x20060000) {
|
|
/* BABT, Rx/Tx FIFO errors */
|
|
mpc5xxx_fec_halt(dev);
|
|
mpc5xxx_fec_init(dev, NULL);
|
|
return 0;
|
|
}
|
|
if (ievent & 0x80000000) {
|
|
/* Heartbeat error */
|
|
fec->eth->x_cntrl |= 0x00000001;
|
|
}
|
|
if (ievent & 0x10000000) {
|
|
/* Graceful stop complete */
|
|
if (fec->eth->x_cntrl & 0x00000001) {
|
|
mpc5xxx_fec_halt(dev);
|
|
fec->eth->x_cntrl &= ~0x00000001;
|
|
mpc5xxx_fec_init(dev, NULL);
|
|
}
|
|
}
|
|
|
|
if (!(pRbd->status & FEC_RBD_EMPTY)) {
|
|
if ((pRbd->status & FEC_RBD_LAST) && !(pRbd->status & FEC_RBD_ERR) &&
|
|
((pRbd->dataLength - 4) > 14)) {
|
|
|
|
/*
|
|
* Get buffer address and size
|
|
*/
|
|
frame = (NBUF *)pRbd->dataPointer;
|
|
frame_length = pRbd->dataLength - 4;
|
|
|
|
#if (DEBUG & 0x20)
|
|
{
|
|
int i;
|
|
printf("recv data hdr:");
|
|
for (i = 0; i < 14; i++)
|
|
printf("%x ", *(frame->head + i));
|
|
printf("\n");
|
|
}
|
|
#endif
|
|
/*
|
|
* Fill the buffer and pass it to upper layers
|
|
*/
|
|
memcpy(buff, frame->head, 14);
|
|
memcpy(buff + 14, frame->data, frame_length);
|
|
NetReceive(buff, frame_length);
|
|
len = frame_length;
|
|
}
|
|
/*
|
|
* Reset buffer descriptor as empty
|
|
*/
|
|
mpc5xxx_fec_rbd_clean(fec, pRbd);
|
|
}
|
|
SDMA_CLEAR_IEVENT (FEC_RECV_TASK_NO);
|
|
return len;
|
|
}
|
|
|
|
|
|
/********************************************************************/
|
|
int mpc5xxx_fec_initialize(bd_t * bis)
|
|
{
|
|
mpc5xxx_fec_priv *fec;
|
|
struct eth_device *dev;
|
|
char *tmp, *end;
|
|
char env_enetaddr[6];
|
|
int i;
|
|
|
|
fec = (mpc5xxx_fec_priv *)malloc(sizeof(*fec));
|
|
dev = (struct eth_device *)malloc(sizeof(*dev));
|
|
memset(dev, 0, sizeof *dev);
|
|
|
|
fec->eth = (ethernet_regs *)MPC5XXX_FEC;
|
|
fec->tbdBase = (FEC_TBD *)FEC_BD_BASE;
|
|
fec->rbdBase = (FEC_RBD *)(FEC_BD_BASE + FEC_TBD_NUM * sizeof(FEC_TBD));
|
|
#if defined(CONFIG_MPC5xxx_FEC_MII100)
|
|
fec->xcv_type = MII100;
|
|
#elif defined(CONFIG_MPC5xxx_FEC_MII10)
|
|
fec->xcv_type = MII10;
|
|
#elif defined(CONFIG_MPC5xxx_FEC_SEVENWIRE)
|
|
fec->xcv_type = SEVENWIRE;
|
|
#else
|
|
#error fec->xcv_type not initialized.
|
|
#endif
|
|
if (fec->xcv_type != SEVENWIRE) {
|
|
/*
|
|
* Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
|
|
* and do not drop the Preamble.
|
|
* No MII for 7-wire mode
|
|
*/
|
|
fec->eth->mii_speed = (((gd->arch.ipb_clk >> 20) / 5) << 1);
|
|
}
|
|
|
|
dev->priv = (void *)fec;
|
|
dev->iobase = MPC5XXX_FEC;
|
|
dev->init = mpc5xxx_fec_init;
|
|
dev->halt = mpc5xxx_fec_halt;
|
|
dev->send = mpc5xxx_fec_send;
|
|
dev->recv = mpc5xxx_fec_recv;
|
|
|
|
sprintf(dev->name, "FEC");
|
|
eth_register(dev);
|
|
|
|
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
|
|
miiphy_register (dev->name,
|
|
fec5xxx_miiphy_read, fec5xxx_miiphy_write);
|
|
#endif
|
|
|
|
/*
|
|
* Try to set the mac address now. The fec mac address is
|
|
* a garbage after reset. When not using fec for booting
|
|
* the Linux fec driver will try to work with this garbage.
|
|
*/
|
|
tmp = getenv("ethaddr");
|
|
if (tmp) {
|
|
for (i=0; i<6; i++) {
|
|
env_enetaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
|
|
if (tmp)
|
|
tmp = (*end) ? end+1 : end;
|
|
}
|
|
mpc5xxx_fec_set_hwaddr(fec, env_enetaddr);
|
|
}
|
|
|
|
return 1;
|
|
}
|
|
|
|
/* MII-interface related functions */
|
|
/********************************************************************/
|
|
int fec5xxx_miiphy_read(const char *devname, uint8 phyAddr, uint8 regAddr, uint16 * retVal)
|
|
{
|
|
ethernet_regs *eth = (ethernet_regs *)MPC5XXX_FEC;
|
|
uint32 reg; /* convenient holder for the PHY register */
|
|
uint32 phy; /* convenient holder for the PHY */
|
|
int timeout = 0xffff;
|
|
|
|
/*
|
|
* reading from any PHY's register is done by properly
|
|
* programming the FEC's MII data register.
|
|
*/
|
|
reg = regAddr << FEC_MII_DATA_RA_SHIFT;
|
|
phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
|
|
|
|
eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | phy | reg);
|
|
|
|
/*
|
|
* wait for the related interrupt
|
|
*/
|
|
while ((timeout--) && (!(eth->ievent & 0x00800000))) ;
|
|
|
|
if (timeout == 0) {
|
|
#if (DEBUG & 0x2)
|
|
printf ("Read MDIO failed...\n");
|
|
#endif
|
|
return -1;
|
|
}
|
|
|
|
/*
|
|
* clear mii interrupt bit
|
|
*/
|
|
eth->ievent = 0x00800000;
|
|
|
|
/*
|
|
* it's now safe to read the PHY's register
|
|
*/
|
|
*retVal = (uint16) eth->mii_data;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/********************************************************************/
|
|
int fec5xxx_miiphy_write(const char *devname, uint8 phyAddr, uint8 regAddr, uint16 data)
|
|
{
|
|
ethernet_regs *eth = (ethernet_regs *)MPC5XXX_FEC;
|
|
uint32 reg; /* convenient holder for the PHY register */
|
|
uint32 phy; /* convenient holder for the PHY */
|
|
int timeout = 0xffff;
|
|
|
|
reg = regAddr << FEC_MII_DATA_RA_SHIFT;
|
|
phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
|
|
|
|
eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
|
|
FEC_MII_DATA_TA | phy | reg | data);
|
|
|
|
/*
|
|
* wait for the MII interrupt
|
|
*/
|
|
while ((timeout--) && (!(eth->ievent & 0x00800000))) ;
|
|
|
|
if (timeout == 0) {
|
|
#if (DEBUG & 0x2)
|
|
printf ("Write MDIO failed...\n");
|
|
#endif
|
|
return -1;
|
|
}
|
|
|
|
/*
|
|
* clear MII interrupt bit
|
|
*/
|
|
eth->ievent = 0x00800000;
|
|
|
|
return 0;
|
|
}
|