11d14bfb75
Add QSPI Secure Boot target to enable chain of trust Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Signed-off-by: Vinitha Pillai <vinitha.pillai@nxp.com> Reviewed-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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Kconfig | ||
ls1012ardb.c | ||
MAINTAINERS | ||
Makefile | ||
README |
Overview -------- QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance development platform, with a complete debugging environment. The LS1012ARDB board supports the QorIQ LS1012A processor and is optimized to support the high-bandwidth DDR3L memory and a full complement of high-speed SerDes ports. LS1012A SoC Overview -------------------- Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A SoC overview. LS1012ARDB board Overview ----------------------- - SERDES Connections, 4 lanes supporting: - PCI Express - 3.0 - SGMII, SGMII 2.5 - SATA 3.0 - DDR Controller - 16-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s -QSPI: A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select signals to - QSPI NOR flash memory (2 virtual banks) - the QSPI emulator.s - USB 3.0 - one high-speed USB 2.0/3.0 port. - Two enhanced secure digital host controllers: - SDHC1 controller can be connected to onboard SDHC connector - SDHC2 controller: Three dual 1:4 mux/demux devices, 74CBTLV3253DS (U30, U31, U33) drive the SDHC2 signals to eMMC, SDIO WiFi, SPI, and Ardiuno shield - 2 I2C controllers - One SATA onboard connectors - UART - The LS1012A processor consists of two UART controllers, out of which only UART1 is used on RDB. - ARM JTAG support Booting Options --------------- a) QSPI Flash Emu Boot b) QSPI Flash 1 c) QSPI Flash 2 QSPI flash map -------------- Images | Size |QSPI Flash Address ------------------------------------------ RCW + PBI | 1MB | 0x4000_0000 U-boot | 1MB | 0x4010_0000 U-boot Env | 1MB | 0x4020_0000 PPA FIT image | 2MB | 0x4050_0000 Linux ITB | ~53MB | 0x40A0_0000