25a9f9747a
Add a driver for the Xilinx LogiCORE DisplayPort IP core, which is a pure DP transmitter core for Xiling FPGA (no display capabilities). Signed-off-by: Mario Six <mario.six@gdsys.cc>
397 lines
11 KiB
C
397 lines
11 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* logicore_dp_tx_regif.h
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*
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* Register interface definition for XILINX LogiCore DisplayPort v6.1 TX
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* (Source) based on Xilinx dp_v3_1 driver sources
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*
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* (C) Copyright 2016
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* Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
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*/
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#ifndef __GDSYS_LOGICORE_DP_TX_REGIF_H__
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#define __GDSYS_LOGICORE_DP_TX_REGIF_H__
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enum {
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/* link configuration field */
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REG_LINK_BW_SET = 0x000,
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REG_LANE_COUNT_SET = 0x004,
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REG_ENHANCED_FRAME_EN = 0x008,
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REG_TRAINING_PATTERN_SET = 0x00C,
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REG_LINK_QUAL_PATTERN_SET = 0x010,
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REG_SCRAMBLING_DISABLE = 0x014,
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REG_DOWNSPREAD_CTRL = 0x018,
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REG_SOFT_RESET = 0x01C,
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};
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enum {
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/* core enables */
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REG_ENABLE = 0x080,
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REG_ENABLE_MAIN_STREAM = 0x084,
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REG_ENABLE_SEC_STREAM = 0x088,
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REG_FORCE_SCRAMBLER_RESET = 0x0C0,
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REG_MST_CONFIG = 0x0D0,
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REG_LINE_RESET_DISABLE = 0x0F0,
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};
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enum {
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/* core ID */
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REG_VERSION = 0x0F8,
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REG_CORE_ID = 0x0FC,
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};
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enum {
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/* AUX channel interface */
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REG_AUX_CMD = 0x100,
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REG_AUX_WRITE_FIFO = 0x104,
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REG_AUX_ADDRESS = 0x108,
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REG_AUX_CLK_DIVIDER = 0x10C,
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REG_USER_FIFO_OVERFLOW = 0x110,
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REG_INTERRUPT_SIG_STATE = 0x130,
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REG_AUX_REPLY_DATA = 0x134,
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REG_AUX_REPLY_CODE = 0x138,
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REG_AUX_REPLY_COUNT = 0x13C,
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REG_INTERRUPT_STATUS = 0x140,
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REG_INTERRUPT_MASK = 0x144,
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REG_REPLY_DATA_COUNT = 0x148,
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REG_REPLY_STATUS = 0x14C,
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REG_HPD_DURATION = 0x150,
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};
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enum {
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/* main stream attributes for SST / MST STREAM1 */
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REG_STREAM1_MSA_START = 0x180,
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REG_MAIN_STREAM_HTOTAL = 0x180,
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REG_MAIN_STREAM_VTOTAL = 0x184,
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REG_MAIN_STREAM_POLARITY = 0x188,
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REG_MAIN_STREAM_HSWIDTH = 0x18C,
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REG_MAIN_STREAM_VSWIDTH = 0x190,
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REG_MAIN_STREAM_HRES = 0x194,
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REG_MAIN_STREAM_VRES = 0x198,
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REG_MAIN_STREAM_HSTART = 0x19C,
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REG_MAIN_STREAM_VSTART = 0x1A0,
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REG_MAIN_STREAM_MISC0 = 0x1A4,
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REG_MAIN_STREAM_MISC1 = 0x1A8,
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REG_M_VID = 0x1AC,
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REG_TU_SIZE = 0x1B0,
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REG_N_VID = 0x1B4,
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REG_USER_PIXEL_WIDTH = 0x1B8,
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REG_USER_DATA_COUNT_PER_LANE = 0x1BC,
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REG_MAIN_STREAM_INTERLACED = 0x1C0,
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REG_MIN_BYTES_PER_TU = 0x1C4,
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REG_FRAC_BYTES_PER_TU = 0x1C8,
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REG_INIT_WAIT = 0x1CC,
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REG_STREAM1 = 0x1D0,
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REG_STREAM2 = 0x1D4,
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REG_STREAM3 = 0x1D8,
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REG_STREAM4 = 0x1DC,
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};
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enum {
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/* PHY configuration status */
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REG_PHY_CONFIG = 0x200,
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REG_PHY_VOLTAGE_DIFF_LANE_0 = 0x220,
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REG_PHY_VOLTAGE_DIFF_LANE_1 = 0x224,
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REG_PHY_VOLTAGE_DIFF_LANE_2 = 0x228,
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REG_PHY_VOLTAGE_DIFF_LANE_3 = 0x22C,
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REG_PHY_TRANSMIT_PRBS7 = 0x230,
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REG_PHY_CLOCK_SELECT = 0x234,
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REG_PHY_POWER_DOWN = 0x238,
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REG_PHY_PRECURSOR_LANE_0 = 0x23C,
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REG_PHY_PRECURSOR_LANE_1 = 0x240,
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REG_PHY_PRECURSOR_LANE_2 = 0x244,
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REG_PHY_PRECURSOR_LANE_3 = 0x248,
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REG_PHY_POSTCURSOR_LANE_0 = 0x24C,
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REG_PHY_POSTCURSOR_LANE_1 = 0x250,
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REG_PHY_POSTCURSOR_LANE_2 = 0x254,
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REG_PHY_POSTCURSOR_LANE_3 = 0x258,
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REG_PHY_STATUS = 0x280,
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REG_GT_DRP_COMMAND = 0x2A0,
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REG_GT_DRP_READ_DATA = 0x2A4,
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REG_GT_DRP_CHANNEL_STATUS = 0x2A8,
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};
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enum {
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/* DisplayPort audio */
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REG_AUDIO_CONTROL = 0x300,
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REG_AUDIO_CHANNELS = 0x304,
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REG_AUDIO_INFO_DATA = 0x308,
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REG_AUDIO_MAUD = 0x328,
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REG_AUDIO_NAUD = 0x32C,
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REG_AUDIO_EXT_DATA = 0x330,
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};
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enum {
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/* HDCP */
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REG_HDCP_ENABLE = 0x400,
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};
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enum {
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/* main stream attributes for MST STREAM2, 3, and 4 */
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REG_STREAM2_MSA_START = 0x500,
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REG_STREAM3_MSA_START = 0x550,
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REG_STREAM4_MSA_START = 0x5A0,
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REG_VC_PAYLOAD_BUFFER_ADDR = 0x800,
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};
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enum {
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LINK_BW_SET_162GBPS = 0x06,
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LINK_BW_SET_270GBPS = 0x0A,
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LINK_BW_SET_540GBPS = 0x14,
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};
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enum {
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LANE_COUNT_SET_1 = 0x1,
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LANE_COUNT_SET_2 = 0x2,
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LANE_COUNT_SET_4 = 0x4,
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};
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enum {
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TRAINING_PATTERN_SET_OFF = 0x0,
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/* training pattern 1 used for clock recovery */
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TRAINING_PATTERN_SET_TP1 = 0x1,
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/* training pattern 2 used for channel equalization */
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TRAINING_PATTERN_SET_TP2 = 0x2,
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/*
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* training pattern 3 used for channel equalization for cores with DP
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* v1.2
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*/
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TRAINING_PATTERN_SET_TP3 = 0x3,
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};
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enum {
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LINK_QUAL_PATTERN_SET_OFF = 0x0,
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/* D10.2 unscrambled test pattern transmitted */
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LINK_QUAL_PATTERN_SET_D102_TEST = 0x1,
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/* symbol error rate measurement pattern transmitted */
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LINK_QUAL_PATTERN_SET_SER_MES = 0x2,
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/* pseudo random bit sequence 7 transmitted */
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LINK_QUAL_PATTERN_SET_PRBS7 = 0x3,
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};
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enum {
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SOFT_RESET_VIDEO_STREAM1_MASK = 0x00000001,
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SOFT_RESET_VIDEO_STREAM2_MASK = 0x00000002,
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SOFT_RESET_VIDEO_STREAM3_MASK = 0x00000004,
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SOFT_RESET_VIDEO_STREAM4_MASK = 0x00000008,
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SOFT_RESET_AUX_MASK = 0x00000080,
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SOFT_RESET_VIDEO_STREAM_ALL_MASK = 0x0000000F,
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};
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enum {
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MST_CONFIG_MST_EN_MASK = 0x00000001,
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};
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enum {
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LINE_RESET_DISABLE_MASK = 0x1,
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};
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#define AUX_CMD_NBYTES_TRANSFER_MASK 0x0000000F
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#define AUX_CMD_SHIFT 8
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#define AUX_CMD_MASK 0x00000F00
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enum {
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AUX_CMD_I2C_WRITE = 0x0,
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AUX_CMD_I2C_READ = 0x1,
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AUX_CMD_I2C_WRITE_STATUS = 0x2,
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AUX_CMD_I2C_WRITE_MOT = 0x4,
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AUX_CMD_I2C_READ_MOT = 0x5,
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AUX_CMD_I2C_WRITE_STATUS_MOT = 0x6,
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AUX_CMD_WRITE = 0x8,
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AUX_CMD_READ = 0x9,
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};
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#define AUX_CLK_DIVIDER_VAL_MASK 0x00FF
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#define AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_SHIFT 8
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#define AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_MASK 0xFF00
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enum {
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INTERRUPT_SIG_STATE_HPD_STATE_MASK = 0x00000001,
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INTERRUPT_SIG_STATE_REQUEST_STATE_MASK = 0x00000002,
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INTERRUPT_SIG_STATE_REPLY_STATE_MASK = 0x00000004,
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INTERRUPT_SIG_STATE_REPLY_TIMEOUT_MASK = 0x00000008,
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};
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enum {
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AUX_REPLY_CODE_ACK = 0x0,
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AUX_REPLY_CODE_I2C_ACK = 0x0,
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AUX_REPLY_CODE_NACK = 0x1,
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AUX_REPLY_CODE_DEFER = 0x2,
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AUX_REPLY_CODE_I2C_NACK = 0x4,
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AUX_REPLY_CODE_I2C_DEFER = 0x8,
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};
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enum {
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INTERRUPT_STATUS_HPD_IRQ_MASK = 0x00000001,
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INTERRUPT_STATUS_HPD_EVENT_MASK = 0x00000002,
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INTERRUPT_STATUS_REPLY_RECEIVED_MASK = 0x00000004,
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INTERRUPT_STATUS_REPLY_TIMEOUT_MASK = 0x00000008,
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INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK = 0x00000010,
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INTERRUPT_STATUS_EXT_PKT_TXD_MASK = 0x00000020,
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};
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enum {
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INTERRUPT_MASK_HPD_IRQ_MASK = 0x00000001,
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INTERRUPT_MASK_HPD_EVENT_MASK = 0x00000002,
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INTERRUPT_MASK_REPLY_RECEIVED_MASK = 0x00000004,
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INTERRUPT_MASK_REPLY_TIMEOUT_MASK = 0x00000008,
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INTERRUPT_MASK_HPD_PULSE_DETECTED_MASK = 0x00000010,
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INTERRUPT_MASK_EXT_PKT_TXD_MASK = 0x00000020,
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};
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#define REPLY_STATUS_REPLY_STATUS_STATE_SHIFT 4
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#define REPLY_STATUS_REPLY_STATUS_STATE_MASK 0x00000FF0
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enum {
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REPLY_STATUS_REPLY_RECEIVED_MASK = 0x00000001,
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REPLY_STATUS_REPLY_IN_PROGRESS_MASK = 0x00000002,
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REPLY_STATUS_REQUEST_IN_PROGRESS_MASK = 0x00000004,
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REPLY_STATUS_REPLY_ERROR_MASK = 0x00000008,
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};
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#define MAIN_STREAMX_POLARITY_VSYNC_POL_SHIFT 1
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enum {
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MAIN_STREAMX_POLARITY_HSYNC_POL_MASK = 0x00000001,
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MAIN_STREAMX_POLARITY_VSYNC_POL_MASK = 0x00000002,
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};
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enum {
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MAIN_STREAMX_MISC0_SYNC_CLK_MASK = 0x00000001,
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};
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#define MAIN_STREAMX_MISC0_COMPONENT_FORMAT_SHIFT 1
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#define MAIN_STREAMX_MISC0_COMPONENT_FORMAT_MASK 0x00000006
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enum {
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MAIN_STREAMX_MISC0_COMPONENT_FORMAT_RGB = 0x0,
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MAIN_STREAMX_MISC0_COMPONENT_FORMAT_YCBCR422 = 0x1,
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MAIN_STREAMX_MISC0_COMPONENT_FORMAT_YCBCR444 = 0x2,
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};
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#define MAIN_STREAMX_MISC0_DYNAMIC_RANGE_SHIFT 3
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#define MAIN_STREAMX_MISC0_DYNAMIC_RANGE_MASK 0x00000008
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#define MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_SHIFT 4
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#define MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_MASK 0x00000010
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#define MAIN_STREAMX_MISC0_BDC_SHIFT 5
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#define MAIN_STREAMX_MISC0_BDC_MASK 0x000000E0
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enum {
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MAIN_STREAMX_MISC0_BDC_6BPC = 0x0,
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MAIN_STREAMX_MISC0_BDC_8BPC = 0x1,
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MAIN_STREAMX_MISC0_BDC_10BPC = 0x2,
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MAIN_STREAMX_MISC0_BDC_12BPC = 0x3,
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MAIN_STREAMX_MISC0_BDC_16BPC = 0x4,
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};
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enum {
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PHY_CONFIG_PHY_RESET_ENABLE_MASK = 0x0000000,
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PHY_CONFIG_PHY_RESET_MASK = 0x0000001,
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PHY_CONFIG_GTTX_RESET_MASK = 0x0000002,
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PHY_CONFIG_GT_ALL_RESET_MASK = 0x0000003,
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PHY_CONFIG_TX_PHY_PMA_RESET_MASK = 0x0000100,
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PHY_CONFIG_TX_PHY_PCS_RESET_MASK = 0x0000200,
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PHY_CONFIG_TX_PHY_POLARITY_MASK = 0x0000800,
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PHY_CONFIG_TX_PHY_PRBSFORCEERR_MASK = 0x0001000,
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PHY_CONFIG_TX_PHY_POLARITY_IND_LANE_MASK = 0x0010000,
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PHY_CONFIG_TX_PHY_POLARITY_LANE0_MASK = 0x0020000,
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PHY_CONFIG_TX_PHY_POLARITY_LANE1_MASK = 0x0040000,
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PHY_CONFIG_TX_PHY_POLARITY_LANE2_MASK = 0x0080000,
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PHY_CONFIG_TX_PHY_POLARITY_LANE3_MASK = 0x0100000,
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PHY_CONFIG_TX_PHY_8B10BEN_MASK = 0x0200000,
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};
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#define PHY_CONFIG_TX_PHY_LOOPBACK_SHIFT 13
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#define PHY_CONFIG_TX_PHY_LOOPBACK_MASK 0x000E000
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enum {
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PHY_CLOCK_SELECT_162GBPS = 0x1,
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PHY_CLOCK_SELECT_270GBPS = 0x3,
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PHY_CLOCK_SELECT_540GBPS = 0x5,
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};
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enum {
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VS_LEVEL_0 = 0x2,
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VS_LEVEL_1 = 0x5,
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VS_LEVEL_2 = 0x8,
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VS_LEVEL_3 = 0xF,
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VS_LEVEL_OFFSET = 0x4,
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};
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enum {
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PE_LEVEL_0 = 0x00,
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PE_LEVEL_1 = 0x0E,
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PE_LEVEL_2 = 0x14,
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PE_LEVEL_3 = 0x1B,
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};
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enum {
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PHY_STATUS_RESET_LANE_2_3_DONE_SHIFT = 2,
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PHY_STATUS_TX_ERROR_LANE_0_SHIFT = 18,
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PHY_STATUS_TX_BUFFER_STATUS_LANE_1_SHIFT = 20,
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PHY_STATUS_TX_ERROR_LANE_1_SHIFT = 22,
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PHY_STATUS_TX_BUFFER_STATUS_LANE_0_SHIFT = 16,
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PHY_STATUS_TX_BUFFER_STATUS_LANE_2_SHIFT = 24,
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PHY_STATUS_TX_ERROR_LANE_2_SHIFT = 26,
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PHY_STATUS_TX_BUFFER_STATUS_LANE_3_SHIFT = 28,
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PHY_STATUS_TX_ERROR_LANE_3_SHIFT = 30,
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};
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enum {
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PHY_STATUS_RESET_LANE_0_DONE_MASK = 0x00000001,
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PHY_STATUS_RESET_LANE_1_DONE_MASK = 0x00000002,
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PHY_STATUS_RESET_LANE_2_3_DONE_MASK = 0x0000000C,
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PHY_STATUS_PLL_LANE0_1_LOCK_MASK = 0x00000010,
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PHY_STATUS_PLL_LANE2_3_LOCK_MASK = 0x00000020,
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PHY_STATUS_PLL_FABRIC_LOCK_MASK = 0x00000040,
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PHY_STATUS_TX_BUFFER_STATUS_LANE_0_MASK = 0x00030000,
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PHY_STATUS_TX_ERROR_LANE_0_MASK = 0x000C0000,
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PHY_STATUS_TX_BUFFER_STATUS_LANE_1_MASK = 0x00300000,
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PHY_STATUS_TX_ERROR_LANE_1_MASK = 0x00C00000,
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PHY_STATUS_TX_BUFFER_STATUS_LANE_2_MASK = 0x03000000,
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PHY_STATUS_TX_ERROR_LANE_2_MASK = 0x0C000000,
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PHY_STATUS_TX_BUFFER_STATUS_LANE_3_MASK = 0x30000000,
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PHY_STATUS_TX_ERROR_LANE_3_MASK = 0xC0000000,
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};
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#define PHY_STATUS_LANE_0_READY_MASK \
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(PHY_STATUS_RESET_LANE_0_DONE_MASK | \
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PHY_STATUS_PLL_LANE0_1_LOCK_MASK)
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#define PHY_STATUS_LANES_0_1_READY_MASK \
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(PHY_STATUS_LANE_0_READY_MASK | \
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PHY_STATUS_RESET_LANE_1_DONE_MASK)
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/*
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* PHY_STATUS_ALL_LANES_READY_MASK seems to be missing lanes 0 and 1 in
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* Xilinx dp_v3_0 implementation
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*/
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#define PHY_STATUS_ALL_LANES_READY_MASK \
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(PHY_STATUS_LANES_0_1_READY_MASK | \
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PHY_STATUS_RESET_LANE_2_3_DONE_MASK | \
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PHY_STATUS_PLL_LANE2_3_LOCK_MASK)
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/**
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* phy_status_lanes_ready_mask() - Generate phy status ready mask
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* @lane_count: Number of lanes for which to generate a mask
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*
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* Return: The generated phy status ready mask
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*/
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static inline u32 phy_status_lanes_ready_mask(u8 lane_count)
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{
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if (lane_count > 2)
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return PHY_STATUS_ALL_LANES_READY_MASK;
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if (lane_count == 2)
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return PHY_STATUS_LANES_0_1_READY_MASK;
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return PHY_STATUS_LANE_0_READY_MASK;
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}
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#define GT_DRP_COMMAND_DRP_ADDR_MASK 0x000F
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#define GT_DRP_COMMAND_DRP_RW_CMD_MASK 0x0080
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#define GT_DRP_COMMAND_DRP_W_DATA_SHIFT 16
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#define GT_DRP_COMMAND_DRP_W_DATA_MASK 0xFF00
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#define HDCP_ENABLE_BYPASS_DISABLE_MASK 0x0001
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#endif /* __GDSYS_LOGICORE_DP_TX_REGIF_H__ */
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