1d4c83c248
Now that we have converted all x86 boards to use driver model timer, remove these legacy timer codes in the tsc driver. Note this also removes the TSC_CALIBRATION_BYPASS Kconfig option, as it is not needed with driver model. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
427 lines
12 KiB
Plaintext
427 lines
12 KiB
Plaintext
menu "x86 architecture"
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depends on X86
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config SYS_ARCH
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default "x86"
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choice
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prompt "Mainboard vendor"
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default VENDOR_EMULATION
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config VENDOR_COREBOOT
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bool "coreboot"
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config VENDOR_EFI
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bool "efi"
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config VENDOR_EMULATION
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bool "emulation"
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config VENDOR_GOOGLE
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bool "Google"
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config VENDOR_INTEL
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bool "Intel"
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endchoice
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# board-specific options below
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source "board/coreboot/Kconfig"
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source "board/efi/Kconfig"
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source "board/emulation/Kconfig"
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source "board/google/Kconfig"
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source "board/intel/Kconfig"
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# platform-specific options below
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source "arch/x86/cpu/baytrail/Kconfig"
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source "arch/x86/cpu/coreboot/Kconfig"
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source "arch/x86/cpu/ivybridge/Kconfig"
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source "arch/x86/cpu/qemu/Kconfig"
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source "arch/x86/cpu/quark/Kconfig"
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source "arch/x86/cpu/queensbay/Kconfig"
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# architecture-specific options below
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config SYS_MALLOC_F_LEN
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default 0x800
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config RAMBASE
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hex
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default 0x100000
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config XIP_ROM_SIZE
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hex
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depends on X86_RESET_VECTOR
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default ROM_SIZE
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config CPU_ADDR_BITS
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int
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default 36
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config HPET_ADDRESS
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hex
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default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
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config SMM_TSEG
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bool
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default n
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config SMM_TSEG_SIZE
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hex
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config X86_RESET_VECTOR
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bool
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default n
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config RESET_SEG_START
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hex
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depends on X86_RESET_VECTOR
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default 0xffff0000
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config RESET_SEG_SIZE
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hex
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depends on X86_RESET_VECTOR
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default 0x10000
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config RESET_VEC_LOC
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hex
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depends on X86_RESET_VECTOR
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default 0xfffffff0
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config SYS_X86_START16
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hex
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depends on X86_RESET_VECTOR
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default 0xfffff800
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config BOARD_ROMSIZE_KB_512
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bool
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config BOARD_ROMSIZE_KB_1024
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bool
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config BOARD_ROMSIZE_KB_2048
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bool
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config BOARD_ROMSIZE_KB_4096
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bool
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config BOARD_ROMSIZE_KB_8192
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bool
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config BOARD_ROMSIZE_KB_16384
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bool
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choice
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prompt "ROM chip size"
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depends on X86_RESET_VECTOR
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default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512
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default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024
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default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048
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default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096
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default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192
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default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384
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help
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Select the size of the ROM chip you intend to flash U-Boot on.
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The build system will take care of creating a u-boot.rom file
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of the matching size.
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config UBOOT_ROMSIZE_KB_512
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bool "512 KB"
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help
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Choose this option if you have a 512 KB ROM chip.
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config UBOOT_ROMSIZE_KB_1024
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bool "1024 KB (1 MB)"
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help
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Choose this option if you have a 1024 KB (1 MB) ROM chip.
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config UBOOT_ROMSIZE_KB_2048
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bool "2048 KB (2 MB)"
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help
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Choose this option if you have a 2048 KB (2 MB) ROM chip.
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config UBOOT_ROMSIZE_KB_4096
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bool "4096 KB (4 MB)"
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help
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Choose this option if you have a 4096 KB (4 MB) ROM chip.
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config UBOOT_ROMSIZE_KB_8192
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bool "8192 KB (8 MB)"
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help
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Choose this option if you have a 8192 KB (8 MB) ROM chip.
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config UBOOT_ROMSIZE_KB_16384
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bool "16384 KB (16 MB)"
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help
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Choose this option if you have a 16384 KB (16 MB) ROM chip.
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endchoice
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# Map the config names to an integer (KB).
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config UBOOT_ROMSIZE_KB
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int
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default 512 if UBOOT_ROMSIZE_KB_512
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default 1024 if UBOOT_ROMSIZE_KB_1024
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default 2048 if UBOOT_ROMSIZE_KB_2048
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default 4096 if UBOOT_ROMSIZE_KB_4096
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default 8192 if UBOOT_ROMSIZE_KB_8192
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default 16384 if UBOOT_ROMSIZE_KB_16384
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# Map the config names to a hex value (bytes).
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config ROM_SIZE
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hex
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default 0x80000 if UBOOT_ROMSIZE_KB_512
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default 0x100000 if UBOOT_ROMSIZE_KB_1024
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default 0x200000 if UBOOT_ROMSIZE_KB_2048
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default 0x400000 if UBOOT_ROMSIZE_KB_4096
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default 0x800000 if UBOOT_ROMSIZE_KB_8192
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default 0xc00000 if UBOOT_ROMSIZE_KB_12288
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default 0x1000000 if UBOOT_ROMSIZE_KB_16384
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config HAVE_INTEL_ME
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bool "Platform requires Intel Management Engine"
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help
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Newer higher-end devices have an Intel Management Engine (ME)
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which is a very large binary blob (typically 1.5MB) which is
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required for the platform to work. This enforces a particular
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SPI flash format. You will need to supply the me.bin file in
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your board directory.
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config X86_RAMTEST
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bool "Perform a simple RAM test after SDRAM initialisation"
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help
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If there is something wrong with SDRAM then the platform will
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often crash within U-Boot or the kernel. This option enables a
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very simple RAM test that quickly checks whether the SDRAM seems
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to work correctly. It is not exhaustive but can save time by
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detecting obvious failures.
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config HAVE_FSP
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bool "Add an Firmware Support Package binary"
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depends on !EFI
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help
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Select this option to add an Firmware Support Package binary to
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the resulting U-Boot image. It is a binary blob which U-Boot uses
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to set up SDRAM and other chipset specific initialization.
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Note: Without this binary U-Boot will not be able to set up its
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SDRAM so will not boot.
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config FSP_FILE
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string "Firmware Support Package binary filename"
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depends on HAVE_FSP
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default "fsp.bin"
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help
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The filename of the file to use as Firmware Support Package binary
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in the board directory.
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config FSP_ADDR
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hex "Firmware Support Package binary location"
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depends on HAVE_FSP
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default 0xfffc0000
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help
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FSP is not Position Independent Code (PIC) and the whole FSP has to
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be rebased if it is placed at a location which is different from the
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perferred base address specified during the FSP build. Use Intel's
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Binary Configuration Tool (BCT) to do the rebase.
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The default base address of 0xfffc0000 indicates that the binary must
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be located at offset 0xc0000 from the beginning of a 1MB flash device.
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config FSP_TEMP_RAM_ADDR
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hex
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depends on HAVE_FSP
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default 0x2000000
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help
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Stack top address which is used in fsp_init() after DRAM is ready and
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CAR is disabled.
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config FSP_SYS_MALLOC_F_LEN
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hex
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depends on HAVE_FSP
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default 0x100000
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help
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Additional size of malloc() pool before relocation.
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config ENABLE_MRC_CACHE
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bool "Enable MRC cache"
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depends on !EFI && !SYS_COREBOOT
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help
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Enable this feature to cause MRC data to be cached in NV storage
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to be used for speeding up boot time on future reboots and/or
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power cycles.
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config SMP
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bool "Enable Symmetric Multiprocessing"
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default n
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help
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Enable use of more than one CPU in U-Boot and the Operating System
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when loaded. Each CPU will be started up and information can be
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obtained using the 'cpu' command. If this option is disabled, then
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only one CPU will be enabled regardless of the number of CPUs
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available.
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config MAX_CPUS
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int "Maximum number of CPUs permitted"
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depends on SMP
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default 4
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help
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When using multi-CPU chips it is possible for U-Boot to start up
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more than one CPU. The stack memory used by all of these CPUs is
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pre-allocated so at present U-Boot wants to know the maximum
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number of CPUs that may be present. Set this to at least as high
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as the number of CPUs in your system (it uses about 4KB of RAM for
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each CPU).
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config AP_STACK_SIZE
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hex
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depends on SMP
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default 0x1000
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help
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Each additional CPU started by U-Boot requires its own stack. This
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option sets the stack size used by each CPU and directly affects
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the memory used by this initialisation process. Typically 4KB is
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enough space.
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config HAVE_VGA_BIOS
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bool "Add a VGA BIOS image"
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help
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Select this option if you have a VGA BIOS image that you would
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like to add to your ROM.
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config VGA_BIOS_FILE
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string "VGA BIOS image filename"
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depends on HAVE_VGA_BIOS
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default "vga.bin"
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help
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The filename of the VGA BIOS image in the board directory.
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config VGA_BIOS_ADDR
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hex "VGA BIOS image location"
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depends on HAVE_VGA_BIOS
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default 0xfff90000
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help
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The location of VGA BIOS image in the SPI flash. For example, base
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address of 0xfff90000 indicates that the image will be put at offset
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0x90000 from the beginning of a 1MB flash device.
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menu "System tables"
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depends on !EFI && !SYS_COREBOOT
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config GENERATE_PIRQ_TABLE
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bool "Generate a PIRQ table"
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default n
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help
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Generate a PIRQ routing table for this board. The PIRQ routing table
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is generated by U-Boot in the system memory from 0xf0000 to 0xfffff
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at every 16-byte boundary with a PCI IRQ routing signature ("$PIR").
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It specifies the interrupt router information as well how all the PCI
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devices' interrupt pins are wired to PIRQs.
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config GENERATE_SFI_TABLE
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bool "Generate a SFI (Simple Firmware Interface) table"
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help
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The Simple Firmware Interface (SFI) provides a lightweight method
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for platform firmware to pass information to the operating system
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via static tables in memory. Kernel SFI support is required to
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boot on SFI-only platforms. If you have ACPI tables then these are
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used instead.
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U-Boot writes this table in write_sfi_table() just before booting
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the OS.
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For more information, see http://simplefirmware.org
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config GENERATE_MP_TABLE
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bool "Generate an MP (Multi-Processor) table"
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default n
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help
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Generate an MP (Multi-Processor) table for this board. The MP table
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provides a way for the operating system to support for symmetric
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multiprocessing as well as symmetric I/O interrupt handling with
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the local APIC and I/O APIC.
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config GENERATE_ACPI_TABLE
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bool "Generate an ACPI (Advanced Configuration and Power Interface) table"
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default n
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help
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The Advanced Configuration and Power Interface (ACPI) specification
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provides an open standard for device configuration and management
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by the operating system. It defines platform-independent interfaces
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for configuration and power management monitoring.
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config GENERATE_SMBIOS_TABLE
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bool "Generate an SMBIOS (System Management BIOS) table"
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default y
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help
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The System Management BIOS (SMBIOS) specification addresses how
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motherboard and system vendors present management information about
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their products in a standard format by extending the BIOS interface
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on Intel architecture systems.
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Check http://www.dmtf.org/standards/smbios for details.
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endmenu
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config MAX_PIRQ_LINKS
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int
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default 8
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help
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This variable specifies the number of PIRQ interrupt links which are
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routable. On most older chipsets, this is 4, PIRQA through PIRQD.
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Some newer chipsets offer more than four links, commonly up to PIRQH.
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config IRQ_SLOT_COUNT
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int
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default 128
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help
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U-Boot can support up to 254 IRQ slot info in the PIRQ routing table
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which in turns forms a table of exact 4KiB. The default value 128
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should be enough for most boards. If this does not fit your board,
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change it according to your needs.
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config PCIE_ECAM_BASE
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hex
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default 0xe0000000
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help
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This is the memory-mapped address of PCI configuration space, which
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is only available through the Enhanced Configuration Access
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Mechanism (ECAM) with PCI Express. It can be set up almost
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anywhere. Before it is set up, it is possible to access PCI
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configuration space through I/O access, but memory access is more
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convenient. Using this, PCI can be scanned and configured. This
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should be set to a region that does not conflict with memory
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assigned to PCI devices - i.e. the memory and prefetch regions, as
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passed to pci_set_region().
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config PCIE_ECAM_SIZE
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hex
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default 0x10000000
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help
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This is the size of memory-mapped address of PCI configuration space,
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which is only available through the Enhanced Configuration Access
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Mechanism (ECAM) with PCI Express. Each bus consumes 1 MiB memory,
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so a default 0x10000000 size covers all of the 256 buses which is the
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maximum number of PCI buses as defined by the PCI specification.
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config I8259_PIC
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bool
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default y
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help
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Intel 8259 ISA compatible chipset incorporates two 8259 (master and
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slave) interrupt controllers. Include this to have U-Boot set up
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the interrupt correctly.
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config I8254_TIMER
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bool
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default y
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help
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Intel 8254 timer contains three counters which have fixed uses.
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Include this to have U-Boot set up the timer correctly.
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config I8042_KEYB
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default y
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config DM_KEYBOARD
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default y
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source "arch/x86/lib/efi/Kconfig"
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endmenu
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