05f0f269b7
The commit 0dba45864b ("arm: Init the debug UART") calls
debug_uart_init() from crt0.S but it won't work because SOC is not
configured yet. That's why create board_debug_uart_init() which calls
ps7_init() earlier before the first access to UART.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/18e67e02a0c7190839a1ef3a11f3fd6babcf34cc.1645104518.git.michal.simek@xilinx.com
91 lines
1.4 KiB
C
91 lines
1.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2014 - 2017 Xilinx, Inc. Michal Simek
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*/
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#include <common.h>
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#include <debug_uart.h>
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#include <hang.h>
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#include <image.h>
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#include <init.h>
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#include <log.h>
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#include <spl.h>
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#include <asm/io.h>
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#include <asm/spl.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/ps7_init_gpl.h>
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#if defined(CONFIG_DEBUG_UART_BOARD_INIT)
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void board_debug_uart_init(void)
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{
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ps7_init();
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}
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#endif
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void board_init_f(ulong dummy)
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{
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#if !defined(CONFIG_DEBUG_UART_BOARD_INIT)
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ps7_init();
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#endif
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arch_cpu_init();
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}
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#ifdef CONFIG_SPL_BOARD_INIT
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void spl_board_init(void)
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{
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preloader_console_init();
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#if defined(CONFIG_ARCH_EARLY_INIT_R) && defined(CONFIG_SPL_FPGA)
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arch_early_init_r();
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#endif
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board_init();
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}
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#endif
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u32 spl_boot_device(void)
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{
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u32 mode;
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switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
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#ifdef CONFIG_SPL_SPI
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case ZYNQ_BM_QSPI:
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mode = BOOT_DEVICE_SPI;
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break;
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#endif
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case ZYNQ_BM_NAND:
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mode = BOOT_DEVICE_NAND;
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break;
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case ZYNQ_BM_NOR:
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mode = BOOT_DEVICE_NOR;
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break;
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#ifdef CONFIG_SPL_MMC
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case ZYNQ_BM_SD:
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mode = BOOT_DEVICE_MMC1;
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break;
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#endif
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case ZYNQ_BM_JTAG:
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mode = BOOT_DEVICE_RAM;
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break;
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default:
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puts("Unsupported boot mode selected\n");
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hang();
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}
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return mode;
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}
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#ifdef CONFIG_SPL_OS_BOOT
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int spl_start_uboot(void)
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{
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/* boot linux */
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return 0;
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}
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#endif
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void spl_board_prepare_for_boot(void)
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{
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ps7_post_config();
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debug("SPL bye\n");
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}
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