344a0e4367
Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
130 lines
3.3 KiB
Plaintext
130 lines
3.3 KiB
Plaintext
CONFIG_PPC=y
|
|
CONFIG_SYS_TEXT_BASE=0xFE000000
|
|
CONFIG_IDENT_STRING=" hrcon dh 0.01"
|
|
CONFIG_SYS_CLK_FREQ=33333333
|
|
CONFIG_MPC83xx=y
|
|
CONFIG_TARGET_HRCON=y
|
|
CONFIG_SYSTEM_PLL_VCO_DIV_2=y
|
|
CONFIG_SYSTEM_PLL_FACTOR_4_1=y
|
|
CONFIG_CORE_PLL_RATIO_3_1=y
|
|
CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
|
|
CONFIG_TSEC1_MODE_RGMII=y
|
|
CONFIG_TSEC2_MODE_RGMII=y
|
|
CONFIG_BAT0=y
|
|
CONFIG_BAT0_NAME="DDR"
|
|
CONFIG_BAT0_BASE=0x00000000
|
|
CONFIG_BAT0_LENGTH_128_MBYTES=y
|
|
CONFIG_BAT0_ACCESS_RW=y
|
|
CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
|
|
CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
|
|
CONFIG_BAT0_USER_MODE_VALID=y
|
|
CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
|
|
CONFIG_BAT1=y
|
|
CONFIG_BAT1_NAME="IMMRBAR"
|
|
CONFIG_BAT1_BASE=0xE0000000
|
|
CONFIG_BAT1_LENGTH_8_MBYTES=y
|
|
CONFIG_BAT1_ACCESS_RW=y
|
|
CONFIG_BAT1_ICACHE_INHIBITED=y
|
|
CONFIG_BAT1_ICACHE_GUARDED=y
|
|
CONFIG_BAT1_DCACHE_INHIBITED=y
|
|
CONFIG_BAT1_DCACHE_GUARDED=y
|
|
CONFIG_BAT1_USER_MODE_VALID=y
|
|
CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
|
|
CONFIG_BAT2=y
|
|
CONFIG_BAT2_NAME="FLASH"
|
|
CONFIG_BAT2_BASE=0xFE000000
|
|
CONFIG_BAT2_LENGTH_8_MBYTES=y
|
|
CONFIG_BAT2_ACCESS_RW=y
|
|
CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y
|
|
CONFIG_BAT2_DCACHE_INHIBITED=y
|
|
CONFIG_BAT2_DCACHE_GUARDED=y
|
|
CONFIG_BAT2_USER_MODE_VALID=y
|
|
CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
|
|
CONFIG_BAT3=y
|
|
CONFIG_BAT3_NAME="STACK_IN_DCACHE"
|
|
CONFIG_BAT3_BASE=0xE6000000
|
|
CONFIG_BAT3_ACCESS_RW=y
|
|
CONFIG_BAT3_USER_MODE_VALID=y
|
|
CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
|
|
CONFIG_LBLAW0=y
|
|
CONFIG_LBLAW0_BASE=0xFE000000
|
|
CONFIG_LBLAW0_NAME="FLASH"
|
|
CONFIG_LBLAW0_LENGTH_8_MBYTES=y
|
|
CONFIG_LBLAW1=y
|
|
CONFIG_LBLAW1_BASE=0xE0600000
|
|
CONFIG_LBLAW1_NAME="FPGA0"
|
|
CONFIG_LBLAW1_LENGTH_1_MBYTES=y
|
|
CONFIG_ELBC_BR0_OR0=y
|
|
CONFIG_BR0_OR0_NAME="FLASH"
|
|
CONFIG_BR0_OR0_BASE=0xFE000000
|
|
CONFIG_BR0_PORTSIZE_16BIT=y
|
|
CONFIG_OR0_AM_8_MBYTES=y
|
|
CONFIG_OR0_XAM_SET=y
|
|
CONFIG_OR0_SCY_15=y
|
|
CONFIG_OR0_CSNT_EARLIER=y
|
|
CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
|
|
CONFIG_OR0_XACS_EXTENDED=y
|
|
CONFIG_OR0_TRLX_RELAXED=y
|
|
CONFIG_OR0_EHTR_8_CYCLE=y
|
|
CONFIG_ELBC_BR1_OR1=y
|
|
CONFIG_BR1_OR1_NAME="FPGA"
|
|
CONFIG_BR1_OR1_BASE=0xE0600000
|
|
CONFIG_BR1_PORTSIZE_16BIT=y
|
|
CONFIG_OR1_AM_1_MBYTES=y
|
|
CONFIG_OR1_XAM_SET=y
|
|
CONFIG_OR1_SCY_15=y
|
|
CONFIG_OR1_CSNT_EARLIER=y
|
|
CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
|
|
CONFIG_OR1_XACS_EXTENDED=y
|
|
CONFIG_OR1_TRLX_RELAXED=y
|
|
CONFIG_OR1_EHTR_8_CYCLE=y
|
|
CONFIG_HID0_FINAL_EMCP=y
|
|
CONFIG_HID0_FINAL_DPM=y
|
|
CONFIG_HID0_FINAL_ICE=y
|
|
CONFIG_HID2_HBE=y
|
|
CONFIG_SICR_ETSEC1_A_TSEC_GTX_CLK125=y
|
|
CONFIG_SICR_IEEE1588_A_GPIO=y
|
|
CONFIG_SICR_GTM_GPIO=y
|
|
CONFIG_SICR_ETSEC2_GPIO=y
|
|
CONFIG_SICR_GPIOSEL_IEEE1588=y
|
|
CONFIG_SICR_TMSOBI1_2_5_V=y
|
|
CONFIG_SICR_TMSOBI2_2_5_V=y
|
|
CONFIG_ACR_PIPE_DEP_4=y
|
|
CONFIG_ACR_RPTCNT_4=y
|
|
CONFIG_SPCR_TSECEP_3=y
|
|
CONFIG_LCRR_DBYP_PLL_BYPASSED=y
|
|
CONFIG_LCRR_CLKDIV_2=y
|
|
CONFIG_CMD_IOLOOP=y
|
|
CONFIG_FIT=y
|
|
CONFIG_FIT_VERBOSE=y
|
|
CONFIG_OF_BOARD_SETUP=y
|
|
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
|
CONFIG_SYS_EXTRA_OPTIONS="HRCON_DH"
|
|
CONFIG_BOOTDELAY=5
|
|
CONFIG_SYS_CONSOLE_INFO_QUIET=y
|
|
# CONFIG_DISPLAY_BOARDINFO is not set
|
|
CONFIG_BOARD_EARLY_INIT_F=y
|
|
CONFIG_BOARD_EARLY_INIT_R=y
|
|
CONFIG_LAST_STAGE_INIT=y
|
|
CONFIG_HUSH_PARSER=y
|
|
CONFIG_CMD_IMLS=y
|
|
CONFIG_CMD_FPGAD=y
|
|
CONFIG_CMD_I2C=y
|
|
CONFIG_CMD_MMC=y
|
|
CONFIG_CMD_PCI=y
|
|
CONFIG_CMD_MII=y
|
|
CONFIG_CMD_PING=y
|
|
CONFIG_CMD_EXT2=y
|
|
CONFIG_DOS_PARTITION=y
|
|
CONFIG_FSL_ESDHC=y
|
|
CONFIG_MTD_NOR_FLASH=y
|
|
CONFIG_FLASH_CFI_DRIVER=y
|
|
CONFIG_SYS_FLASH_PROTECTION=y
|
|
CONFIG_SYS_FLASH_CFI=y
|
|
CONFIG_PHY_MARVELL=y
|
|
CONFIG_MII=y
|
|
CONFIG_TSEC_ENET=y
|
|
CONFIG_CONS_INDEX=2
|
|
CONFIG_SYS_NS16550=y
|
|
CONFIG_OF_LIBFDT=y
|