Simon Glass 191c008a21 x86: Implement a cache for Memory Reference Code parameters ... The memory reference code takes a very long time to 'train' its SDRAM interface, around half a second. To avoid this delay on every boot we can store the parameters from the last training sessions to speed up the next. Add an implementation of this, storing the training data in CMOS RAM and SPI flash. Signed-off-by: Simon Glass <sjg@chromium.org>		2015-01-24 06:13:45 -07:00
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coreboot	x86: Use ipchecksum from net/	2015-01-24 06:13:44 -07:00
ivybridge	x86: Implement a cache for Memory Reference Code parameters	2015-01-24 06:13:45 -07:00
queensbay	x86: fsp: Drop get_hob_type() and get_hob_length()	2015-01-13 07:25:02 -08:00
call64.S	x86: Add support for starting 64-bit kernel	2014-10-28 20:43:47 -06:00
config.mk	x86: Factor out common values in the link script	2014-11-25 06:33:59 -07:00
cpu.c	x86: Save mtrr support flag in global data	2015-01-23 17:24:55 -07:00
interrupts.c	x86: Drop old CONFIG_INTEL_CORE_ARCH code	2014-11-25 06:34:03 -07:00
lapic.c	x86: Add LAPIC setup code	2014-11-25 06:34:11 -07:00
Makefile	x86: Add support for MTRRs	2015-01-13 07:25:00 -08:00
mtrr.c	x86: Test mtrr support flag before accessing mtrr msr	2015-01-23 17:24:55 -07:00
pci.c	pci: Make pci apis usable before relocation	2015-01-12 17:03:41 -08:00
resetvec.S	Add GPL-2.0+ SPDX-License-Identifier to source files	2013-07-24 09:44:38 -04:00
start16.S	x86: Fix various code format issues in start16.S	2015-01-23 17:24:55 -07:00
start.S	x86: Disable CAR before relocation on platforms that need it	2015-01-13 07:25:01 -08:00
turbo.c	x86: Add Intel speedstep and turbo mode code	2014-11-25 06:34:02 -07:00
u-boot.lds	x86: Factor out common values in the link script	2014-11-25 06:33:59 -07:00