16dad75975
Neither of these parts should have the erratum this is meant to work around. Delete it. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
645 lines
21 KiB
C
645 lines
21 KiB
C
/*
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* Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* mpc8569mds board configuration file
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/* High Level Configuration Options */
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#define CONFIG_BOOKE 1 /* BOOKE */
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#define CONFIG_E500 1 /* BOOKE e500 family */
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#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/68 */
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#define CONFIG_MPC8569 1 /* MPC8569 specific */
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#define CONFIG_MPC8569MDS 1 /* MPC8569MDS board specific */
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#define CONFIG_FSL_ELBC 1 /* Has Enhance localbus controller */
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#define CONFIG_PCI 1 /* Disable PCI/PCIE */
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#define CONFIG_PCIE1 1 /* PCIE controller */
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#define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */
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#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
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#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
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#define CONFIG_QE /* Enable QE */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
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#ifndef __ASSEMBLY__
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extern unsigned long get_clock_freq(void);
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#endif
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/* Replace a call to get_clock_freq (after it is implemented)*/
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#define CONFIG_SYS_CLK_FREQ 66666666
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#define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#ifdef CONFIG_ATM
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#define CONFIG_PQ_MDS_PIB
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#define CONFIG_PQ_MDS_PIB_ATM
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#endif
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/*
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* These can be toggled for performance analysis, otherwise use default.
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*/
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#define CONFIG_L2_CACHE /* toggle L2 cache */
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#define CONFIG_BTB /* toggle branch predition */
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#ifdef CONFIG_NAND
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#define CONFIG_NAND_U_BOOT 1
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#define CONFIG_RAMBOOT_NAND 1
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#ifdef CONFIG_NAND_SPL
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#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
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#else
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#define CONFIG_SYS_TEXT_BASE 0xf8f82000
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#endif
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#endif
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#ifndef CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_TEXT_BASE 0xfff80000
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#endif
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#ifndef CONFIG_SYS_MONITOR_BASE
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
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#endif
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/*
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* Only possible on E500 Version 2 or newer cores.
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*/
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#define CONFIG_ENABLE_36BIT_PHYS 1
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
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#define CONFIG_BOARD_EARLY_INIT_R 1
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#define CONFIG_HWCONFIG
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#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x00400000
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/*
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* Config the L2 Cache as L2 SRAM
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*/
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#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
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#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
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#define CONFIG_SYS_L2_SIZE (512 << 10)
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#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
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/*
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* Base addresses -- Note these are effective addresses where the
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* actual resources get mapped (not physical addresses)
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*/
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#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
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#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR
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/* physical addr of CCSRBAR */
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#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
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/* PQII uses CONFIG_SYS_IMMR */
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#if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL)
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#define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR
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#else
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
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#endif
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/* DDR Setup */
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#define CONFIG_FSL_DDR3
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#undef CONFIG_FSL_DDR_INTERACTIVE
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#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
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#define CONFIG_DDR_SPD
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#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
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#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
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#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
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/* DDR is system memory*/
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
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#define CONFIG_NUM_DDR_CONTROLLERS 1
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#define CONFIG_DIMM_SLOTS_PER_CTLR 1
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#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
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/* I2C addresses of SPD EEPROMs */
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#define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
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#define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */
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/* These are used when DDR doesn't use SPD. */
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#define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1024MB */
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#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
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#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
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#define CONFIG_SYS_DDR_TIMING_3 0x00020000
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#define CONFIG_SYS_DDR_TIMING_0 0x00330004
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#define CONFIG_SYS_DDR_TIMING_1 0x6F6B4644
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#define CONFIG_SYS_DDR_TIMING_2 0x002888D0
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#define CONFIG_SYS_DDR_SDRAM_CFG 0x47000000
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#define CONFIG_SYS_DDR_SDRAM_CFG_2 0x04401040
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#define CONFIG_SYS_DDR_SDRAM_MODE 0x40401521
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#define CONFIG_SYS_DDR_SDRAM_MODE_2 0x8000C000
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#define CONFIG_SYS_DDR_SDRAM_INTERVAL 0x03E00000
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#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
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#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x01000000
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#define CONFIG_SYS_DDR_TIMING_4 0x00220001
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#define CONFIG_SYS_DDR_TIMING_5 0x03402400
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#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600
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#define CONFIG_SYS_DDR_WRLVL_CNTL 0x0655A604
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#define CONFIG_SYS_DDR_CDR_1 0x80040000
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#define CONFIG_SYS_DDR_CDR_2 0x00000000
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#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
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#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
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#define CONFIG_SYS_DDR_CONTROL 0xc7000000 /* Type = DDR3 */
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#define CONFIG_SYS_DDR_CONTROL2 0x24400000
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#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
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#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
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#define CONFIG_SYS_DDR_SBE 0x00010000
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#undef CONFIG_CLOCKS_IN_MHZ
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/*
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* Local Bus Definitions
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*/
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#define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */
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#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_BCSR_BASE 0xf8000000
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#define CONFIG_SYS_BCSR_BASE_PHYS CONFIG_SYS_BCSR_BASE
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/*Chip select 0 - Flash*/
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#define CONFIG_FLASH_BR_PRELIM 0xfe000801
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#define CONFIG_FLASH_OR_PRELIM 0xfe000ff7
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/*Chip select 1 - BCSR*/
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#define CONFIG_SYS_BR1_PRELIM 0xf8000801
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#define CONFIG_SYS_OR1_PRELIM 0xffffe9f7
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/*Chip select 4 - PIB*/
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#define CONFIG_SYS_BR4_PRELIM 0xf8008801
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#define CONFIG_SYS_OR4_PRELIM 0xffffe9f7
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/*Chip select 5 - PIB*/
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#define CONFIG_SYS_BR5_PRELIM 0xf8010801
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#define CONFIG_SYS_OR5_PRELIM 0xffffe9f7
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
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#undef CONFIG_SYS_FLASH_CHECKSUM
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#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
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#if defined(CONFIG_RAMBOOT_NAND)
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#define CONFIG_SYS_RAMBOOT
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#define CONFIG_SYS_EXTRA_ENV_RELOC
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#else
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#undef CONFIG_SYS_RAMBOOT
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#endif
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_SYS_FLASH_EMPTY_INFO
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/* Chip select 3 - NAND */
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#ifndef CONFIG_NAND_SPL
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#define CONFIG_SYS_NAND_BASE 0xFC000000
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#else
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#define CONFIG_SYS_NAND_BASE 0xFFF00000
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#endif
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/* NAND boot: 4K NAND loader config */
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#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
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#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
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#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
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#define CONFIG_SYS_NAND_U_BOOT_START \
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(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
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#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
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#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
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#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
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#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
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#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, }
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_MTD_NAND_VERIFY_WRITE 1
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#define CONFIG_CMD_NAND 1
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#define CONFIG_NAND_FSL_ELBC 1
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#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
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#define CONFIG_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \
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| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
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| BR_PS_8 /* Port Size = 8 bit */ \
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| BR_MS_FCM /* MSEL = FCM */ \
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| BR_V) /* valid */
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#define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
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| OR_FCM_CSCT \
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| OR_FCM_CST \
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| OR_FCM_CHT \
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| OR_FCM_SCY_1 \
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| OR_FCM_TRLX \
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| OR_FCM_EHTR)
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#ifdef CONFIG_RAMBOOT_NAND
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#define CONFIG_SYS_BR0_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
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#define CONFIG_SYS_OR0_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
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#define CONFIG_SYS_BR3_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
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#define CONFIG_SYS_OR3_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
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#else
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#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
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#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
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#define CONFIG_SYS_BR3_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
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#define CONFIG_SYS_OR3_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
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#endif
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#define CONFIG_SYS_LBC_LCRR 0x00000004 /* LB clock ratio reg */
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#define CONFIG_SYS_LBC_LBCR 0x00040000 /* LB config reg */
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#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
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#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
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#define CONFIG_SYS_INIT_RAM_LOCK 1
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#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
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#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
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#define CONFIG_SYS_GBL_DATA_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
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#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
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/* Serial Port */
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_SERIAL_MULTI 1
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
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#ifdef CONFIG_NAND_SPL
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#define CONFIG_NS16550_MIN_FUNCTIONS
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#endif
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
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/* Use the HUSH parser*/
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#define CONFIG_SYS_HUSH_PARSER
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#ifdef CONFIG_SYS_HUSH_PARSER
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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#endif
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/* pass open firmware flat tree */
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#define CONFIG_OF_LIBFDT 1
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#define CONFIG_OF_BOARD_SETUP 1
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#define CONFIG_OF_STDOUT_VIA_ALIAS 1
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/*
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* I2C
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*/
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#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
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#define CONFIG_HARD_I2C /* I2C with hardware support*/
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#undef CONFIG_SOFT_I2C /* I2C bit-banged */
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#define CONFIG_I2C_MULTI_BUS
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#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CONFIG_SYS_I2C_SLAVE 0x7F
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#define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */
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#define CONFIG_SYS_I2C_OFFSET 0x3000
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#define CONFIG_SYS_I2C2_OFFSET 0x3100
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/*
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* I2C2 EEPROM
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*/
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#define CONFIG_ID_EEPROM
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#ifdef CONFIG_ID_EEPROM
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#define CONFIG_SYS_I2C_EEPROM_NXID
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#endif
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
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#define CONFIG_SYS_EEPROM_BUS_NUM 1
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#define PLPPAR1_I2C_BIT_MASK 0x0000000F
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#define PLPPAR1_I2C2_VAL 0x00000000
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#define PLPPAR1_ESDHC_VAL 0x0000000A
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#define PLPDIR1_I2C_BIT_MASK 0x0000000F
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#define PLPDIR1_I2C2_VAL 0x0000000F
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#define PLPDIR1_ESDHC_VAL 0x00000006
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#define PLPPAR1_UART0_BIT_MASK 0x00000fc0
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#define PLPPAR1_ESDHC_4BITS_VAL 0x00000a80
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#define PLPDIR1_UART0_BIT_MASK 0x00000fc0
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#define PLPDIR1_ESDHC_4BITS_VAL 0x00000a80
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/*
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* General PCI
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* Memory Addresses are mapped 1-1. I/O is mapped from 0
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*/
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#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
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#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
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#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
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#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
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#define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000
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#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
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#define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000
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#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
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#define CONFIG_SYS_SRIO_MEM_VIRT 0xc0000000
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#define CONFIG_SYS_SRIO_MEM_BUS 0xc0000000
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#define CONFIG_SYS_SRIO_MEM_PHYS 0xc0000000
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#ifdef CONFIG_QE
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/*
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* QE UEC ethernet configuration
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*/
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#define CONFIG_SYS_UCC_RGMII_MODE /* Set UCC work at RGMII by default */
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#undef CONFIG_SYS_UCC_RMII_MODE /* Set UCC work at RMII mode */
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#define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120)
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#define CONFIG_UEC_ETH
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#define CONFIG_ETHPRIME "UEC0"
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#define CONFIG_PHY_MODE_NEED_CHANGE
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#define CONFIG_UEC_ETH1 /* GETH1 */
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#define CONFIG_HAS_ETH0
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#ifdef CONFIG_UEC_ETH1
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#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
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#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE
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#if defined(CONFIG_SYS_UCC_RGMII_MODE)
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#define CONFIG_SYS_UEC1_TX_CLK QE_CLK12
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#define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH
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#define CONFIG_SYS_UEC1_PHY_ADDR 7
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#define CONFIG_SYS_UEC1_INTERFACE_TYPE RGMII_ID
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#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
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#elif defined(CONFIG_SYS_UCC_RMII_MODE)
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#define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 /* CLK16 for RMII */
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#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
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#define CONFIG_SYS_UEC1_PHY_ADDR 8 /* 0x8 for RMII */
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#define CONFIG_SYS_UEC1_INTERFACE_TYPE RMII
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#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
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#endif /* CONFIG_SYS_UCC_RGMII_MODE */
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#endif /* CONFIG_UEC_ETH1 */
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#define CONFIG_UEC_ETH2 /* GETH2 */
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#define CONFIG_HAS_ETH1
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#ifdef CONFIG_UEC_ETH2
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#define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */
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#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE
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#if defined(CONFIG_SYS_UCC_RGMII_MODE)
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#define CONFIG_SYS_UEC2_TX_CLK QE_CLK17
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#define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH
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#define CONFIG_SYS_UEC2_PHY_ADDR 1
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#define CONFIG_SYS_UEC2_INTERFACE_TYPE RGMII_ID
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#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
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#elif defined(CONFIG_SYS_UCC_RMII_MODE)
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#define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 /* CLK 16 for RMII */
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#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
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#define CONFIG_SYS_UEC2_PHY_ADDR 0x9 /* 0x9 for RMII */
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#define CONFIG_SYS_UEC2_INTERFACE_TYPE RMII
|
|
#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
|
|
#endif /* CONFIG_SYS_UCC_RGMII_MODE */
|
|
#endif /* CONFIG_UEC_ETH2 */
|
|
|
|
#define CONFIG_UEC_ETH3 /* GETH3 */
|
|
#define CONFIG_HAS_ETH2
|
|
|
|
#ifdef CONFIG_UEC_ETH3
|
|
#define CONFIG_SYS_UEC3_UCC_NUM 2 /* UCC3 */
|
|
#define CONFIG_SYS_UEC3_RX_CLK QE_CLK_NONE
|
|
#if defined(CONFIG_SYS_UCC_RGMII_MODE)
|
|
#define CONFIG_SYS_UEC3_TX_CLK QE_CLK12
|
|
#define CONFIG_SYS_UEC3_ETH_TYPE GIGA_ETH
|
|
#define CONFIG_SYS_UEC3_PHY_ADDR 2
|
|
#define CONFIG_SYS_UEC3_INTERFACE_TYPE RGMII_ID
|
|
#define CONFIG_SYS_UEC3_INTERFACE_SPEED 1000
|
|
#elif defined(CONFIG_SYS_UCC_RMII_MODE)
|
|
#define CONFIG_SYS_UEC3_TX_CLK QE_CLK16 /* CLK_16 for RMII */
|
|
#define CONFIG_SYS_UEC3_ETH_TYPE FAST_ETH
|
|
#define CONFIG_SYS_UEC3_PHY_ADDR 0xA /* 0xA for RMII */
|
|
#define CONFIG_SYS_UEC3_INTERFACE_TYPE RMII
|
|
#define CONFIG_SYS_UEC3_INTERFACE_SPEED 100
|
|
#endif /* CONFIG_SYS_UCC_RGMII_MODE */
|
|
#endif /* CONFIG_UEC_ETH3 */
|
|
|
|
#define CONFIG_UEC_ETH4 /* GETH4 */
|
|
#define CONFIG_HAS_ETH3
|
|
|
|
#ifdef CONFIG_UEC_ETH4
|
|
#define CONFIG_SYS_UEC4_UCC_NUM 3 /* UCC4 */
|
|
#define CONFIG_SYS_UEC4_RX_CLK QE_CLK_NONE
|
|
#if defined(CONFIG_SYS_UCC_RGMII_MODE)
|
|
#define CONFIG_SYS_UEC4_TX_CLK QE_CLK17
|
|
#define CONFIG_SYS_UEC4_ETH_TYPE GIGA_ETH
|
|
#define CONFIG_SYS_UEC4_PHY_ADDR 3
|
|
#define CONFIG_SYS_UEC4_INTERFACE_TYPE RGMII_ID
|
|
#define CONFIG_SYS_UEC4_INTERFACE_SPEED 1000
|
|
#elif defined(CONFIG_SYS_UCC_RMII_MODE)
|
|
#define CONFIG_SYS_UEC4_TX_CLK QE_CLK16 /* CLK16 for RMII */
|
|
#define CONFIG_SYS_UEC4_ETH_TYPE FAST_ETH
|
|
#define CONFIG_SYS_UEC4_PHY_ADDR 0xB /* 0xB for RMII */
|
|
#define CONFIG_SYS_UEC4_INTERFACE_TYPE RMII
|
|
#define CONFIG_SYS_UEC4_INTERFACE_SPEED 100
|
|
#endif /* CONFIG_SYS_UCC_RGMII_MODE */
|
|
#endif /* CONFIG_UEC_ETH4 */
|
|
|
|
#undef CONFIG_UEC_ETH6 /* GETH6 */
|
|
#define CONFIG_HAS_ETH5
|
|
|
|
#ifdef CONFIG_UEC_ETH6
|
|
#define CONFIG_SYS_UEC6_UCC_NUM 5 /* UCC6 */
|
|
#define CONFIG_SYS_UEC6_RX_CLK QE_CLK_NONE
|
|
#define CONFIG_SYS_UEC6_TX_CLK QE_CLK_NONE
|
|
#define CONFIG_SYS_UEC6_ETH_TYPE GIGA_ETH
|
|
#define CONFIG_SYS_UEC6_PHY_ADDR 4
|
|
#define CONFIG_SYS_UEC6_INTERFACE_TYPE SGMII
|
|
#define CONFIG_SYS_UEC6_INTERFACE_SPEED 1000
|
|
#endif /* CONFIG_UEC_ETH6 */
|
|
|
|
#undef CONFIG_UEC_ETH8 /* GETH8 */
|
|
#define CONFIG_HAS_ETH7
|
|
|
|
#ifdef CONFIG_UEC_ETH8
|
|
#define CONFIG_SYS_UEC8_UCC_NUM 7 /* UCC8 */
|
|
#define CONFIG_SYS_UEC8_RX_CLK QE_CLK_NONE
|
|
#define CONFIG_SYS_UEC8_TX_CLK QE_CLK_NONE
|
|
#define CONFIG_SYS_UEC8_ETH_TYPE GIGA_ETH
|
|
#define CONFIG_SYS_UEC8_PHY_ADDR 6
|
|
#define CONFIG_SYS_UEC8_INTERFACE_TYPE SGMII
|
|
#define CONFIG_SYS_UEC8_INTERFACE_SPEED 1000
|
|
#endif /* CONFIG_UEC_ETH8 */
|
|
|
|
#endif /* CONFIG_QE */
|
|
|
|
#if defined(CONFIG_PCI)
|
|
|
|
#define CONFIG_NET_MULTI
|
|
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
|
|
|
#undef CONFIG_EEPRO100
|
|
#undef CONFIG_TULIP
|
|
#define CONFIG_E1000 /* Define e1000 pci Ethernet card */
|
|
|
|
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
|
|
|
#endif /* CONFIG_PCI */
|
|
|
|
#ifndef CONFIG_NET_MULTI
|
|
#define CONFIG_NET_MULTI 1
|
|
#endif
|
|
|
|
/*
|
|
* Environment
|
|
*/
|
|
#if defined(CONFIG_SYS_RAMBOOT)
|
|
#if defined(CONFIG_RAMBOOT_NAND)
|
|
#define CONFIG_ENV_IS_IN_NAND 1
|
|
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
|
|
#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
|
|
#endif
|
|
#else
|
|
#define CONFIG_ENV_IS_IN_FLASH 1
|
|
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
|
|
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
|
|
#define CONFIG_ENV_SIZE 0x2000
|
|
#endif
|
|
|
|
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
|
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
|
|
|
/* QE microcode/firmware address */
|
|
#define CONFIG_SYS_QE_FW_ADDR 0xfff00000
|
|
|
|
/*
|
|
* BOOTP options
|
|
*/
|
|
#define CONFIG_BOOTP_BOOTFILESIZE
|
|
#define CONFIG_BOOTP_BOOTPATH
|
|
#define CONFIG_BOOTP_GATEWAY
|
|
#define CONFIG_BOOTP_HOSTNAME
|
|
|
|
|
|
/*
|
|
* Command line configuration.
|
|
*/
|
|
#include <config_cmd_default.h>
|
|
|
|
#define CONFIG_CMD_PING
|
|
#define CONFIG_CMD_I2C
|
|
#define CONFIG_CMD_MII
|
|
#define CONFIG_CMD_ELF
|
|
#define CONFIG_CMD_IRQ
|
|
#define CONFIG_CMD_SETEXPR
|
|
#define CONFIG_CMD_REGINFO
|
|
|
|
#if defined(CONFIG_PCI)
|
|
#define CONFIG_CMD_PCI
|
|
#endif
|
|
|
|
|
|
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
|
|
|
#define CONFIG_MMC 1
|
|
|
|
#ifdef CONFIG_MMC
|
|
#define CONFIG_FSL_ESDHC
|
|
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
|
|
#define CONFIG_CMD_MMC
|
|
#define CONFIG_GENERIC_MMC
|
|
#define CONFIG_CMD_EXT2
|
|
#define CONFIG_CMD_FAT
|
|
#define CONFIG_DOS_PARTITION
|
|
#endif
|
|
|
|
/*
|
|
* Miscellaneous configurable options
|
|
*/
|
|
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
|
#define CONFIG_CMDLINE_EDITING /* Command-line editing */
|
|
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
|
|
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
|
|
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
|
|
#if defined(CONFIG_CMD_KGDB)
|
|
#define CONFIG_SYS_CBSIZE 2048 /* Console I/O Buffer Size */
|
|
#else
|
|
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
|
|
#endif
|
|
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
|
|
/* Print Buffer Size */
|
|
#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
|
|
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
|
|
/* Boot Argument Buffer Size */
|
|
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
|
|
|
|
/*
|
|
* For booting Linux, the board info and command line data
|
|
* have to be in the first 16 MB of memory, since this is
|
|
* the maximum mapped by the Linux kernel during initialization.
|
|
*/
|
|
#define CONFIG_SYS_BOOTMAPSZ (16 << 20)
|
|
/* Initial Memory map for Linux*/
|
|
|
|
#if defined(CONFIG_CMD_KGDB)
|
|
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
|
|
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
|
|
#endif
|
|
|
|
/*
|
|
* Environment Configuration
|
|
*/
|
|
#define CONFIG_HOSTNAME mpc8569mds
|
|
#define CONFIG_ROOTPATH /nfsroot
|
|
#define CONFIG_BOOTFILE your.uImage
|
|
|
|
#define CONFIG_SERVERIP 192.168.1.1
|
|
#define CONFIG_GATEWAYIP 192.168.1.1
|
|
#define CONFIG_NETMASK 255.255.255.0
|
|
|
|
#define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/
|
|
|
|
#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
|
|
#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
|
|
|
|
#define CONFIG_BAUDRATE 115200
|
|
|
|
#define CONFIG_EXTRA_ENV_SETTINGS \
|
|
"netdev=eth0\0" \
|
|
"consoledev=ttyS0\0" \
|
|
"ramdiskaddr=600000\0" \
|
|
"ramdiskfile=your.ramdisk.u-boot\0" \
|
|
"fdtaddr=400000\0" \
|
|
"fdtfile=your.fdt.dtb\0" \
|
|
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
|
"nfsroot=$serverip:$rootpath " \
|
|
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
|
|
"console=$consoledev,$baudrate $othbootargs\0" \
|
|
"ramargs=setenv bootargs root=/dev/ram rw " \
|
|
"console=$consoledev,$baudrate $othbootargs\0" \
|
|
|
|
#define CONFIG_NFSBOOTCOMMAND \
|
|
"run nfsargs;" \
|
|
"tftp $loadaddr $bootfile;" \
|
|
"tftp $fdtaddr $fdtfile;" \
|
|
"bootm $loadaddr - $fdtaddr"
|
|
|
|
#define CONFIG_RAMBOOTCOMMAND \
|
|
"run ramargs;" \
|
|
"tftp $ramdiskaddr $ramdiskfile;" \
|
|
"tftp $loadaddr $bootfile;" \
|
|
"bootm $loadaddr $ramdiskaddr"
|
|
|
|
#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
|
|
|
|
#endif /* __CONFIG_H */
|